公开(公告)号：US08143166B2

公开(公告)日：2012-03-27

申请号：US12046151

申请日：2008-03-11

申请人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

发明人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

IPC分类号： H01L21/461

CPC分类号： H01L21/31053 ,  H01L21/3212

摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.

摘要翻译： 在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。 在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。 惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。 增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。 抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。

公开(公告)号：US20090233444A1

公开(公告)日：2009-09-17

申请号：US12046151

申请日：2008-03-11

申请人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

发明人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

IPC分类号： H01L21/306 ,  C09K13/00

CPC分类号： H01L21/31053 ,  H01L21/3212

摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.

摘要翻译： 在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。 在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。 惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。 增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。 抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。

公开(公告)号：US20080051008A1

公开(公告)日：2008-02-28

申请号：US11466133

申请日：2006-08-22

申请人： Laertis Economikos ,  Deok-Kee Kim ,  Byeongju Park

发明人： Laertis Economikos ,  Deok-Kee Kim ,  Byeongju Park

IPC分类号： B24B49/00 ,  B24B7/30 ,  B24B29/00

CPC分类号： B24B37/042 ,  B24B1/005

摘要： A chemical mechanical polishing (CMP) apparatus includes a workpiece carrier configured for retaining a workpiece thereupon, a polishing platen configured for retaining a polishing pad thereupon, and an electromagnetic coil surrounding a periphery of the workpiece carrier. The electromagnetic coil is configured to provide a magnetic field of alternating polarity to cause the rotation of ferromagnetic slurry particles disposed on the workpiece to facilitate polishing of the workpiece.

摘要翻译： 化学机械抛光（CMP）装置包括构造成用于保持其上的工件的工件载体，被配置为用于将抛光垫保持在其上的抛光台和围绕工件载体的周边的电磁线圈。 电磁线圈被配置成提供具有交替极性的磁场，以引起设置在工件上的铁磁性浆料颗粒的旋转，以便于抛光工件。

公开(公告)号：US20050079709A1

公开(公告)日：2005-04-14

申请号：US10605610

申请日：2003-10-13

申请人： Donald Delehanty ,  James Hannah ,  Daniel Heenan ,  Fen Jamin ,  Laertis Economikos

发明人： Donald Delehanty ,  James Hannah ,  Daniel Heenan ,  Fen Jamin ,  Laertis Economikos

IPC分类号： B24B7/22 ,  B24B37/04 ,  C09G1/04 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/461

CPC分类号： C09G1/04 ,  B24B7/228 ,  H01L21/31053

摘要： Disclosed herein are a system and method of polishing a layer of a substrate. The disclosed method includes providing a polishing apparatus adapted to impart relative movement between a polishing pad and a substrate having a first layer to be polished; providing a liquid medium having a pH between 4 and 11 to an interface between the substrate and the polishing pad, the liquid medium including a pH controlling substance including at least one of an acid and a base, a carbonate and a stabilizer additive comprising at least one selected from the group consisting of amino acids and polyacrylic acid; and moving at least one of the substrate and the polishing pad relative to the other to polish the layer of the substrate.

摘要翻译： 本文公开了一种抛光衬底层的系统和方法。 所公开的方法包括提供适于在抛光垫和具有要抛光的第一层的基底之间施加相对运动的抛光装置; 提供pH在4和11之间的液体介质到基底和抛光垫之间的界面，液体介质包括pH控制物质，其包括酸和碱中的至少一种，碳酸盐和稳定剂添加剂，至少包括 一个选自氨基酸和聚丙烯酸; 并且相对于另一个移动衬底和抛光垫中的至少一个以抛光衬底的层。

公开(公告)号：US06794242B1

公开(公告)日：2004-09-21

申请号：US09675435

申请日：2000-09-29

申请人： Thomas W. Dyer ,  Andreas Knorr ,  Laertis Economikos ,  Scott Halle ,  Rajeev Malik ,  Norbert Arnod

发明人： Thomas W. Dyer ,  Andreas Knorr ,  Laertis Economikos ,  Scott Halle ,  Rajeev Malik ,  Norbert Arnod

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10891

摘要： A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride remaining in place. Once the devices have been formed and the gate polysilicon has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide fills the regions between and on top of the polysilicon plugs. The Top Oxide is than planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.

摘要翻译： 如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。 顶部氧化物通过首先形成垂直装置而形成，其中衬垫氮化物保持就位。 一旦器件已经形成并且栅极多晶硅已经被平坦化到衬底氮化物的表面之下，衬垫氮化物被剥离掉，留下栅极多晶硅插塞的顶部延伸到活性硅表面之上。 这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。 沉积的顶部氧化物填充多晶硅插塞之间和之上的区域。 顶部氧化物被平坦化回到多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。 顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。

公开(公告)号：US06656817B2

公开(公告)日：2003-12-02

申请号：US10136097

申请日：2002-04-30

申请人： Ramachandra Divakaruni ,  Laertis Economikos ,  Byeong Y. Kim

发明人： Ramachandra Divakaruni ,  Laertis Economikos ,  Byeong Y. Kim

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/76229 ,  H01L21/763

摘要： Disclosed herein is a method of filling isolation trenches in a substrate. The method includes anisotropically etching trenches in a surface of a substrate and partially filling the trenches with a deposited oxide. As a consequence of the deposition, the oxide accumulates in mounds on the surface between trenches. The trenches are then filled with a supporting material of a highly flowable material such as anti-reflective coating (ARC), low-K dielectric, or a spin-on-polymer, or alternatively, a supporting material of polysilicon. A flattening process is then applied to lower the mound topography. The supporting material is then removed and the filling of the trenches with oxide is then continued. When polysilicon is used as the supporting material, the mounds are removed by wet etching prior to removing the polysilicon.

摘要翻译： 本文公开了一种在衬底中填充隔离沟槽的方法。 该方法包括在衬底的表面中各向异性蚀刻沟槽，并用沉积的氧化物部分地填充沟槽。 作为沉积的结果，氧化物堆积在沟槽之间的表面上的土堆中。 然后用诸如抗反射涂层（ARC），低K电介质或旋涂聚合物的高度可流动的材料的支撑材料或者多晶硅的支撑材料填充沟槽。 然后应用扁平化过程以降低墩形地形。 然后移除支撑材料，然后继续用氧化物填充沟槽。 当使用多晶硅作为支撑材料时，在去除多晶硅之前通过湿法蚀刻去除土堆。

公开(公告)号：US06596580B2

公开(公告)日：2003-07-22

申请号：US09982574

申请日：2001-10-18

申请人： Jingyu Lian ,  Greg Costrini ,  Laertis Economikos ,  Michael Wise

发明人： Jingyu Lian ,  Greg Costrini ,  Laertis Economikos ,  Michael Wise

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L27/10855

摘要： The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited with a barrier layer.

摘要翻译： 将底层电极和阻挡层之间的界面暴露于高温氧气环境下，通过原位沉积有阻挡层的Pt进行避免。

公开(公告)号：US06403412B1

公开(公告)日：2002-06-11

申请号：US09304291

申请日：1999-05-03

申请人： Laertis Economikos ,  Byeongju Park

发明人： Laertis Economikos ,  Byeongju Park

IPC分类号： H01L218234

CPC分类号： H01L27/1087 ,  H01L21/3065 ,  H01L21/76232

摘要： A method fabricates a bottle shaped trench by providing a substrate with a substantially vertical trench therein and a collar about an upper interior portion of the trench and isotropically HCl etching a lower interior portion of the trench under the collar for expansion thereof, wherein the expanded lower interior portion has a wider cross section than that of the upper interior portion of the trench. Further, the method performs potential in-situ process integration with a gas phase doping in the same tool as the one that performed the gas phase etching process.

摘要翻译： 一种方法是通过在其中提供基本上垂直的沟槽的衬底和围绕沟槽的上部内部的套环来制造瓶形沟槽，并且各向同性地在衬套下蚀刻沟槽的下部内部以使其膨胀，其中扩大的下部 内部部分具有比沟槽的上部内部部分更宽的横截面。 此外，该方法在与执行气相蚀刻工艺的工具相同的工具中进行与气相掺杂的潜在的原位工艺集成。

公开(公告)号：US06368969B1

公开(公告)日：2002-04-09

申请号：US09607350

申请日：2000-06-30

申请人： Laertis Economikos ,  Fen Fen Jamin

发明人： Laertis Economikos ,  Fen Fen Jamin

IPC分类号： H01L21302

CPC分类号： H01L21/3212

摘要： The polishing uniformity of a material on a substrate is improved by using a polishing method where an applied pressure on the backside of the substrate is changed during the polishing process. The method is especially useful for polishing thin material layers requiring precise control of polishing across the substrate, e.g., for TaSiN layers used in the formation of gate stacks and stacked capacitors.

摘要翻译： 通过使用在抛光处理中改变衬底背面施加的压力而改变衬底的材料的抛光均匀性得到改善。 该方法对于抛光需要精确控制衬底上的抛光的薄材料层是特别有用的，例如用于形成栅叠层和叠层电容器的TaSiN层。

公开(公告)号：US06319794B1

公开(公告)日：2001-11-20

申请号：US09172697

申请日：1998-10-14

申请人： Hiroyuki Akatsu ,  Tze-Chiang Chen ,  Laertis Economikos ,  Herbert L. Ho ,  Richard Kleinhenz ,  Jack A. Mandelman ,  Wesley C. Natzle

发明人： Hiroyuki Akatsu ,  Tze-Chiang Chen ,  Laertis Economikos ,  Herbert L. Ho ,  Richard Kleinhenz ,  Jack A. Mandelman ,  Wesley C. Natzle

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill material. The intersection of the structure and the semiconductor surface in which it is formed, is free of silicon nitride, but the isolation structure may include a silicon nitride liner which is within the trench and recessed below the semiconductor surface.

摘要翻译： 一种用于半导体器件的浅沟槽隔离结构和用于在半导体衬底内制造浅沟槽隔离器件的方法。 浅沟槽隔离结构是无凹槽的，并且包括未退火的介电材料作为沟槽填充材料。 其结构与其形成的半导体表面的交叉点不含氮化硅，但是隔离结构可以包括位于沟槽内并凹陷在半导体表面下方的氮化硅衬垫。