利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.01 秒)

    Method of fabricating strained channel devices
    3.
    发明申请
    Method of fabricating strained channel devices 失效
    应变通道器件的制造方法

    公开(公告)号：US20060226483A1

    公开(公告)日：2006-10-12

    申请号：US11100206

    申请日：2005-04-06

    申请人： Patrick Lo ,  Lakshmi Bera ,  Wei Loh ,  Balakumar Subramanian ,  Narayanan Balasubramanian

    发明人： Patrick Lo ,  Lakshmi Bera ,  Wei Loh ,  Balakumar Subramanian ,  Narayanan Balasubramanian

    IPC分类号： H01L27/12 ,  H01L21/20

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78687

    摘要： A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer. A second embodiment of this invention features the thinning of a portion of the semiconductor alloy layer prior to the oxidation procedure allowing a lower level of germanium to be segregated into a first underlying portion of the underlying single crystalline silicon body, while during the same oxidation procedure a second portion of the underlying single crystalline silicon body receives a higher level of germanium segregation. So the subsequently deposited silicon-germanium layer, although the same process and thickness, can be strained in different states (tensile or compressive) and levels, depending different underlying portions' germanium concentration.

    摘要翻译： 已经开发了用于形成拉伸和压缩应变硅层以适应MOSFET或CMOS器件的沟道区的工艺。 在形成浅沟槽隔离结构以及施加高温氧化和激活程序之后，开始用于获得应变硅层的制造顺序。 沉积半导体合金层，然后沉积氧化工序，将锗组分从上覆的半导体合金层分离成下面的单晶硅体。 分离到下面的单晶硅体中的锗的水平决定了随后选择性生长的硅层的拉伸状态的应变水平。 本发明的第二个实施方案的特征在于在氧化过程之前使半导体合金层的一部分变薄，允许较低水平的锗分离成下面的单晶硅体的第一下面部分，同时在相同的氧化过程 底层单晶硅体的第二部分接受较高水平的锗分离。 因此，随后沉积的硅 - 锗层，尽管相同的工艺和厚度，可以根据不同的下层部分的锗浓度在不同的状态（拉伸或压缩）和水平应变。

    Gate Electrode Architecture for Improved Work Function Tuning and Method of Manufacture
    4.
    发明申请
    Gate Electrode Architecture for Improved Work Function Tuning and Method of Manufacture 失效
    用于改进工作功能的门电极结构调整和制造方法

    公开(公告)号：US20050275035A1

    公开(公告)日：2005-12-15

    申请号：US11160126

    申请日：2005-06-09

    申请人： Shajan Mathew ,  Lakshmi Bera ,  Narayanan Balasubramanian

    发明人： Shajan Mathew ,  Lakshmi Bera ,  Narayanan Balasubramanian

    IPC分类号： H01L21/8238 ,  H01L29/772

    CPC分类号： H01L21/823842

    摘要： A method of forming gate electrodes having different work functions includes forming a first well of a first conductivity type and a second well of a second conductivity type. Subsequently, a gate dielectric layer is deposited over the first and second wells. A multi-layer stack comprising two or more thin metal/metal nitride layers is next formed over the first well. A thick metal/metal nitride layer is formed over the multi-layer stack to form the first gate electrode. The thick metal/metal nitride layer is also formed over the gate dielectric layer portion extending over the second well, thereby forming the second gate electrode. The first and second electrodes are then annealed, and thereafter exhibit different work functions as desired.

    摘要翻译： 形成具有不同功函数的栅电极的方法包括形成第一导电类型的第一阱和第二导电类型的第二阱。 随后，栅极电介质层沉积在第一和第二阱上。 包括两个或多个薄金属/金属氮化物层的多层堆叠接着形成在第一阱上。 在多层叠层上形成厚金属/金属氮化物层以形成第一栅电极。 厚金属/金属氮化物层也形成在在第二阱上延伸的栅极电介质层部分上，从而形成第二栅电极。 然后将第一和第二电极退火，然后根据需要显示不同的功函数。

    Salicide process for metal gate CMOS devices
    5.
    发明申请
    Salicide process for metal gate CMOS devices 审中-公开
    金属栅极CMOS器件的自杀处理

    公开(公告)号：US20050164460A1

    公开(公告)日：2005-07-28

    申请号：US10763304

    申请日：2004-01-23

    申请人： Shajan Mathew ,  Lakshmi Bera

    发明人： Shajan Mathew ,  Lakshmi Bera

    IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

    摘要： A process of forming metal silicide on specific regions of a MOSFET device without degrading a MOSFET metal gate structure during a wet etch cycle of a self-aligned metal silicide (SALICIDE) procedure, has been developed. The process features protecting or encapsulating the metal gate structure prior to a wet etch procedure used to remove unreacted metal after metal silicide formation. This is accomplished via use of an amorphous silicon shape initially defined on an underlying metal gate structure, allowing the salicide procedure to form metal silicide on the top surface of the gate structure. The metal gate structure now featuring an overlying metal silicide shape and featuring overlying composite insulator sidewall spacers, can be subjected to a salicide wet etch procedure without risk of metal gate erosion.

    摘要翻译： 已经开发了在自对准金属硅化物（SALICIDE）程序的湿蚀刻循环期间在MOSFET器件的特定区域上形成金属硅化物而不降低MOSFET金属栅极结构的工艺。 该方法特征是在用于在金属硅化物形成之后去除未反应的金属的湿蚀刻方法之前保护或封装金属栅极结构。 这通过使用最初限定在下面的金属栅极结构上的非晶硅形状来实现，允许自对准硅化物工艺在栅极结构的顶表面上形成金属硅化物。 现在具有覆盖金属硅化物形状并具有覆盖复合绝缘子侧壁间隔物的金属栅极结构可以经受自对准湿法蚀刻程序而没有金属栅侵蚀的风险。