摘要:
A system for implementing a memory column redundancy scheme is provided. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.
摘要:
Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204) of an integrated circuit (200). The voltage controller adjusts the gate signal depending upon whether the circuitry is in an eFuse programming mode or an eFuse resistance measuring mode. The voltage controller may optionally include a voltage tuner (252) for tuning the gate signal to account for operating variations in the programming transistor caused by manufacturing variations.
摘要:
Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204) of an integrated circuit (200). The voltage controller adjusts the gate signal depending upon whether the circuitry is in an eFuse programming mode or an eFuse resistance measuring mode. The voltage controller may optionally include a voltage tuner (252) for tuning the gate signal to account for operating variations in the programming transistor caused by manufacturing variations.
摘要:
A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and ordering the cells in each group from one extreme to the other extreme value of a featured parameter for which the integrated circuit is to be tested. Each one of the cells in the library have a known value of another parameter so that the substitution of a library cell for an original cell or another library cell does not affect the overall integrated circuit value for that known parameter. A substitution can thus be made with the knowledge that additional problems involving the known parameter are not being created. If a test of the integrated circuit discovers a problem in a particular cell's performance with regard to the featured parameter the appropriate library group is accessed and the failing cell is replaced with the first unused cell in the group. The process is repeated until the integrated circuit passes a performance test.
摘要:
An apparatus for improving storage latch susceptibility to single event upsets includes a dual interconnected storage cell (DICE) configured within a storage latch circuit; a pair of separate three-state circuits configured to write the DICE latch, with each three-state circuit coupled to separate data nodes within the DICE latch; and a pair of local clock circuits configured within the storage latch circuit, the pair of local clock circuits configured to generate a duplicate pair of control signals that separately control a corresponding one of the separate three-state circuits. In the event of a charge accumulation event on only one of the pair of local clock circuits so as to change the logical state of the corresponding control signal, the presence of the other of the pair of local clock circuits that remains unaffected by the charge accumulation event prevents an error in the logical state of the DICE latch.
摘要:
An electronic fuse structure is disclosed for integrated circuits that is programmable with low voltage and incorporates a differential sensing scheme. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse caused by the sense operation. During the sense operation a gating transistor emulates the voltage drop across a fuse select transistor for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse is also disclosed.
摘要:
An oscillator circuit on a chip with a single I/O node whose output generally corresponds to a performance level of the IC chip. The single I/O node provides an easy access and testing point for evaluating chip performance. The I/O node is used for coupling to the oscillator circuit, and for activating and monitoring its oscillating output signal. The single I/O node may be accessed at the wafer level, after packaging, or in the field.
摘要:
A method and system of modeling power leakage for a design comprises providing one or more cell libraries comprising parameters for particular device characteristics and providing a module configured to determine of cell leakages of a device for a PVT corner. In determining the cell leakage, the module uses the device characteristics contained in the one or more cell libraries, in combination with one or more components at a PVT for a predetermined application and an amount of devices in a leakage path (Fckt) and a leakage distribution (Fchip). There is no need to recharacterize the one or more cell libraries.
摘要:
An unclocked electrically programmable fuse (eFUSE) system includes at least two resistive voltage dividers, one voltage divider including an eFUSE, and a differential amplifier. An output node of at least one of the voltage dividers includes an eFUSE that changes an output voltage based on a state of the eFUSE, and the differential amplifier changes the output voltage into a digital output with no clocking capabilities.
摘要:
A method and system of modeling power leakage for a design comprises providing one or more cell libraries comprising parameters for particular device characteristics and providing a module configured to determine of cell leakages of a device for a PVT corner. In determining the cell leakage, the module uses the device characteristics contained in the one or more cell libraries, in combination with one or more components at a PVT for a predetermined application and an amount of devices in a leakage path (Fckt) and a leakage distribution (Fchip). There is no need to recharacterize the one or more cell libraries.