公开(公告)号：US06530997B1

公开(公告)日：2003-03-11

申请号：US09543484

申请日：2000-04-06

申请人： Steven C. Avanzino ,  Larry Yu Wang

发明人： Steven C. Avanzino ,  Larry Yu Wang

IPC分类号： B08B704

CPC分类号： C23C14/022

摘要： A method and article of manufacture of a semiconductor device having a cleaned source/drain surface and substantially uniform cobalt silicide deposited thereon. The method of the invention includes a precursor conventional step of an argon ion pre-sputter step which generally cleans the semiconductor device surfaces but ensures a resputtering of SiO2 to form SiOx species deposits on the source/drain surface of the device. An in situ treatment using silicon hydride species causes reduction of the SiOx species leaving a cleaned residual silicon which can accept a cobalt deposition to form a desired cobalt silicide layer on the source/drain surface.

摘要翻译： 具有清洁的源极/漏极表面和沉积在其上的基本均匀的硅化钴的半导体器件的方法和制品。 本发明的方法包括氩离子预溅射步骤的前体常规步骤，其通常清洁半导体器件表面，但是确保SiO 2的再溅射以在器件的源极/漏极表面上形成SiO x物质沉积物。 使用硅氢化物物质的原位处理导致SiO x物质的还原，留下清洁的剩余硅，其可以接受钴沉积以在源极/漏极表面上形成期望的钴硅化物层。

公开(公告)号：US06232635B1

公开(公告)日：2001-05-15

申请号：US09543991

申请日：2000-04-06

申请人： Larry Yu Wang ,  Steven C. Avanzino ,  Jeffrey A. Shields ,  Stephen Keetai Park

发明人： Larry Yu Wang ,  Steven C. Avanzino ,  Jeffrey A. Shields ,  Stephen Keetai Park

IPC分类号： H01L291788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.

摘要翻译： 制造半导体闪存单元的制品和方法。 该方法包括在硅衬底上制造隔离层，在隔离层上形成氧化物，在其上生长隧道氧化物层，沉积第一多晶硅层，掩蔽和蚀刻第一多晶硅层，沉积第二多晶硅 层并进行覆盖层回蚀步骤，形成形成第三多晶硅层的氧化物/氮化物/氧化物层并在其上沉积硅化物层。

公开(公告)号：US5926723A

公开(公告)日：1999-07-20

申请号：US813008

申请日：1997-03-04

申请人： Larry Yu Wang

发明人： Larry Yu Wang

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/31056

摘要： A method of forming an improved planarization mask for shallow trench isolation process area in integrated circuit manufacturing is disclosed. The planarization mask is generated automatically by using actual mask data as a reference. The invention discloses an algorithm which measures the geometric and relative separation distances of the active areas and performs the necessary merging, deletion and differential biasing to produce the planarization mask which has relaxed geometric boundaries, thereby allowing low cost and simplified manufacturing.

摘要翻译： 公开了一种在集成电路制造中形成用于浅沟槽隔离处理区域的改进的平坦化掩模的方法。 通过使用实际的掩模数据作为参考，自动生成平面化掩模。 本发明公开了一种测量有源区域的几何相对间隔距离并执行必要的合并，删除和微分偏置以产生具有松弛的几何边界的平面化掩模的算法，从而允许低成本和简化的制造。

公开(公告)号：US5893744A

公开(公告)日：1999-04-13

申请号：US789255

申请日：1997-01-28

申请人： Larry Yu Wang

发明人： Larry Yu Wang

IPC分类号： H01L21/762 ,  H01L23/544 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L21/76229 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

摘要： A method of forming an alignment mark in a wafer during the manufacture of shallow isolation trenches for semiconductor devices provides a nitride layer on a substrate prior to the formation of the alignment mark. Once the nitride layer has been formed, etching is performed to create the alignment mark in the substrate. Further processing steps of the shallow trench isolation technique do not require the depositing of nitride into the alignment mark. Since the alignment mark is etched only after the nitride layer has been deposited, no further nitride enters into the alignment mark and a nitride-free alignment mark is provided.

摘要翻译： 在制造用于半导体器件的浅隔离沟槽期间在晶片中形成对准标记的方法在形成对准标记之前在衬底上提供氮化物层。 一旦形成了氮化物层，就进行蚀刻以在衬底中产生对准标记。 浅沟槽隔离技术的其他处理步骤不需要将氮化物沉积到对准标记中。 由于只有在沉积氮化物层之后蚀刻对准标记，所以不会进一步的氮化物进入对准标记，并且不提供无氮化物的对准标记。

公开(公告)号：US06265273B1

公开(公告)日：2001-07-24

申请号：US09359502

申请日：1999-07-23

申请人： Steven C. Avanzino ,  Stephen Keetai Park ,  Bharath Rangarajan ,  Jeffrey A. Shields ,  Larry Yu Wang ,  Guarionex Morales

发明人： Steven C. Avanzino ,  Stephen Keetai Park ,  Bharath Rangarajan ,  Jeffrey A. Shields ,  Larry Yu Wang ,  Guarionex Morales

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/31116

摘要： A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.

摘要翻译： 本文公开了一种在集成电路中形成间隔物的方法。 该方法包括在半导体衬底上提供栅极结构，在栅极结构的侧面附近沉积间隔物材料，并蚀刻间隔物材料以形成间隔物。 间隔物具有暴露于直接溅射的最小表面积。

公开(公告)号：US6087243A

公开(公告)日：2000-07-11

申请号：US955449

申请日：1997-10-21

申请人： Larry Yu Wang

发明人： Larry Yu Wang

IPC分类号： H01L21/762 ,  H01L21/8234

CPC分类号： H01L21/76229 ,  H01L21/823481 ,  Y10S438/911

摘要： The quality of an ultra thin gate oxide film, particularly at the edges of a shallow trench isolation structure, is improved employing a double sacrificial oxide technique. After trench filling and planarization, the pad oxide layer thickness is increased during trench fill densification in an oxidizing atmosphere. The pad oxide is then removed exposing the substrate surface and trench edges. A second sacrificial oxide is formed consuming part of the substrate surface. The second sacrificial oxide is then removed along with defects in the substrate surface prior to gate oxide and gate electrode formation.

摘要翻译： 使用双重牺牲氧化物技术改进了超薄栅极氧化膜的质量，特别是在浅沟槽隔离结构的边缘处的质量。 在沟槽填充和平坦化之后，在氧化气氛中的沟槽填充致密化期间，衬垫氧化物层厚度增加。 然后去除衬垫氧化物，暴露衬底表面和沟槽边缘。 形成消耗部分基板表面的第二牺牲氧化物。 然后在栅极氧化物和栅电极形成之前，将第二牺牲氧化物与衬底表面中的缺陷一起除去。

公开(公告)号：US5963816A

公开(公告)日：1999-10-05

申请号：US982072

申请日：1997-12-01

申请人： Larry Yu Wang ,  Craig Sander ,  Anna Minvielle

发明人： Larry Yu Wang ,  Craig Sander ,  Anna Minvielle

IPC分类号： H01L21/762 ,  H01L23/544 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L21/76224 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002

摘要： The separate formation of alignment marks and manufacturing a semiconductor device comprising photolithographically printing circuit patterns is avoided by utilizing trenches formed when etching to form shallow isolation trenches, thereby increasing manufacturing throughput and reducing costs. Embodiments include utilizing alignment trenches having a depth of about 2,400.ANG. to less than about 4,000.ANG., e.g., 3,000.ANG., formed substantially simultaneously with forming isolation trenches having substantially the same depth as the alignment trenches.

摘要翻译： 通过利用在蚀刻时形成的沟槽形成浅隔离沟槽，从而避免了制造包括光刻印刷电路图形的半导体器件的单独形成，从而提高了制造量并降低了成本。 实施例包括使用具有大约2,400安培的深度的对准沟槽，以小于约4,000安培，例如3,000安培，其基本上同时形成，形成具有与对准沟槽基本相同的深度的隔离沟槽。