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    EFFICIENT COMPONENT MAPPING FOR PROGRAMABLE LOGIC DEVICES, SYSTEMS, AND METHODS
    1.
    发明申请
    EFFICIENT COMPONENT MAPPING FOR PROGRAMABLE LOGIC DEVICES, SYSTEMS, AND METHODS 有权

    公开(公告)号：US20250068818A1

    公开(公告)日：2025-02-27

    申请号：US18810215

    申请日：2024-08-20

    Applicant: Lattice Semiconductor Corporation

    Inventor： Michael Schneider ,  Eileen Shen ,  Chih-Chung Chen

    IPC: G06F30/373 ,  G06F30/392

    Abstract: Various techniques are provided for efficiently mapping synthesized components to physical hardware components of a PLD. In one example, a method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The method also includes converting the operations to a plurality of synthesized components. The method also includes mapping a selected one of the synthesized components to a model associated with first and second types of hardware components of the PLD. The selected synthesized component is compatible with first and second specifications of the first and second types of hardware components, respectively. The method also includes assigning the selected synthesized component to a physical location of the PLD comprising either the first type of hardware component or the second type of hardware component to improve a performance metric of the PLD configured with the design. Additional devices, systems and methods are also provided.

    Fast boot systems and methods for programmable logic devices
    3.
    发明授权
    Fast boot systems and methods for programmable logic devices 有权

    公开(公告)号：US11681536B2

    公开(公告)日：2023-06-20

    申请号：US16706591

    申请日：2019-12-06

    Applicant: Lattice Semiconductor Corporation

    Inventor： Fulong Zhang ,  John Gordon Hands ,  Wei Han ,  Mark Everhard

    IPC: G06F9/445 ,  G06F1/26 ,  G06F9/4401

    CPC classification number: G06F9/44505 ,  G06F1/26 ,  G06F9/4401

    Abstract: Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided.

    Power supply regulation for programmable logic devices
    4.
    发明授权
    Power supply regulation for programmable logic devices 有权

    公开(公告)号：US11316521B2

    公开(公告)日：2022-04-26

    申请号：US17115560

    申请日：2020-12-08

    Applicant: Lattice Semiconductor Corporation

    Inventor： Loren McLaury

    IPC: H03K19/17772 ,  H03K19/1776

    Abstract: Various techniques are provided to implement power supply regulation for programmable logic devices (PLDs). In one example, a method includes powering configuration memory cells of a PLD with a first voltage. The method further includes configuring the configuration memory cells while the configuration memory cells are powered by the first voltage. The method further includes operating the PLD while the configuration memory cells are powered with a second voltage higher than the first voltage. The method further includes powering the configuration memory cells with a third voltage lower than the first voltage in response to an indication to transition the PLD to a sleep mode of the PLD. Related systems and devices are provided.

    FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
    6.
    发明申请
    FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 有权

    公开(公告)号：US20220012064A1

    公开(公告)日：2022-01-13

    申请号：US17485104

    申请日：2021-09-24

    Applicant: Lattice Semiconductor Corporation

    Inventor： Fulong Zhang ,  Gordon Hands ,  Satwant Singh ,  Wei Han ,  Ravindar Lall ,  Joel Coplen ,  Sreepada Hegade ,  Ming Hui Ding

    IPC: G06F9/4401 ,  H03K19/17756 ,  H03K19/17758 ,  G06F3/06 ,  G06F9/445 ,  G06F21/57

    Abstract: Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.

    Network repository for metadata
    7.
    发明授权
    Network repository for metadata 有权

    公开(公告)号：US11138150B2

    公开(公告)日：2021-10-05

    申请号：US15799977

    申请日：2017-10-31

    Applicant: Lattice Semiconductor Corporation

    Inventor： Brian K. Schmidt ,  James G. Hanko ,  J. Duane Northcutt

    IPC: G06F15/16 ,  G06F16/13 ,  G06F16/48

    Abstract: A method and apparatus for a network repository for metadata. Embodiments of a data repository include a memory to store data including one or more data content items, where each data content item is associated with zero or more metadata items, and where each data content item is associated with a handle and each metadata item is associated with an attribute name. The data repository further includes a network interface configured to communicate with a client device, and a control unit configured to control the storage of data in the memory, where the control unit provides functions for writing data to and reading data from the memory and where the control unit is to transfer the data without interpretation.

    Adaptive processing of video streams with reduced color resolution
    8.
    再颁专利
    Adaptive processing of video streams with reduced color resolution 有权

    公开(公告)号：USRE48740E1

    公开(公告)日：2021-09-14

    申请号：US16460966

    申请日：2019-07-02

    Applicant: Lattice Semiconductor Corporation

    Inventor： Laurence Alan Thompson

    IPC: H04N19/00 ,  H04N19/186 ,  H04N19/196 ,  H04N19/85 ,  H04N19/136 ,  H04N19/172

    Abstract: A solution for adaptively processing a digital image with reduced color resolution is described herein. A source device pre-processes a video frame with reduce color resolution by remapping luma components and chroma components of the video frame, and encodes the pre-processed video frame. The source device remaps a half of luma components on a scan line of the video frame onto a data channel of a source line to an encoder and remaps the other half of the luma components on the scan line to another data channel of the source line. The source device remaps the corresponding chroma components onto a third data channel of a source line. By using a data channel conventionally configured to transmit chroma components, the solution enables a video codec to adaptively encode a digital image with reduced color resolution without converting the digital image to full color resolution before the encoding.

    POWER SUPPLY REGULATION FOR PROGRAMMABLE LOGIC DEVICES
    9.
    发明申请
    POWER SUPPLY REGULATION FOR PROGRAMMABLE LOGIC DEVICES 有权

    公开(公告)号：US20210175888A1

    公开(公告)日：2021-06-10

    申请号：US17115560

    申请日：2020-12-08

    Applicant: Lattice Semiconductor Corporation

    Inventor： Loren McLaury

    IPC: H03K19/17772 ,  H03K19/1776

    Abstract: Various techniques are provided to implement power supply regulation for programmable logic devices (PLDs). In one example, a method includes powering configuration memory cells of a PLD with a first voltage. The method further includes configuring the configuration memory cells while the configuration memory cells are powered by the first voltage. The method further includes operating the PLD while the configuration memory cells are powered with a second voltage higher than the first voltage. The method further includes powering the configuration memory cells with a third voltage lower than the first voltage in response to an indication to transition the PLD to a sleep mode of the PLD. Related systems and devices are provided.

    LOW-SPEED BUS TIME STAMP METHODS AND CIRCUITRY
    10.
    发明申请
    LOW-SPEED BUS TIME STAMP METHODS AND CIRCUITRY 审中-公开

    公开(公告)号：US20200019209A1

    公开(公告)日：2020-01-16

    申请号：US16581715

    申请日：2019-09-24

    Applicant: Lattice Semiconductor Corporation

    Inventor： Bradley Sharpe-Geisler

    IPC: G06F1/12 ,  H04L7/04 ,  H04J3/06 ,  G06F13/42

    Abstract: Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.

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