公开(公告)号：US07435685B2

公开(公告)日：2008-10-14

申请号：US11531493

申请日：2006-09-13

申请人： Gerardo A. Delgadino ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

发明人： Gerardo A. Delgadino ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

IPC分类号： H01L21/311

CPC分类号： H01L21/76826 ,  H01L21/76811 ,  H01L21/76813

摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

摘要翻译： 一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。

公开(公告)号：US07422776B2

公开(公告)日：2008-09-09

申请号：US11149826

申请日：2005-06-10

申请人： Kang Sub Yim ,  Lihua Li Huang ,  Francimar Schmitt ,  Li-Qun Xia

发明人： Kang Sub Yim ,  Lihua Li Huang ,  Francimar Schmitt ,  Li-Qun Xia

IPC分类号： H05H1/24

CPC分类号： H01L21/02126 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02203 ,  H01L21/02304 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76835

摘要： Low K dielectric films exhibiting low mechanical stress may be formed utilizing various techniques in accordance with the present invention. In one embodiment, carbon-containing silicon oxide films are formed by plasma-assisted chemical vapor deposition at low temperatures (300° C. or less). In accordance with another embodiment, as-deposited carbon containing silicon oxide films incorporate a porogen whose subsequent liberation reduces film stress.

摘要翻译： 可以使用根据本发明的各种技术来形成表现出低机械应力的低K电介质膜。 在一个实施方案中，通过在低温（300℃或更低）下的等离子体辅助化学气相沉积形成含碳氧化硅膜。 根据另一个实施方案，沉积的含碳氧化硅膜含有致孔剂，其随后的释放降低膜应力。

公开(公告)号：US20080145998A1

公开(公告)日：2008-06-19

申请号：US11531493

申请日：2006-09-13

申请人： GERARDO A. DELGADINO ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

发明人： GERARDO A. DELGADINO ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

IPC分类号： H01L21/76

CPC分类号： H01L21/76826 ,  H01L21/76811 ,  H01L21/76813

摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

摘要翻译： 一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔是 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。

公开(公告)号：US20120009803A1

公开(公告)日：2012-01-12

申请号：US13212153

申请日：2011-08-17

申请人： Kee Bum Jung ,  Dale R. Du Bois ,  Lun Tsuei ,  Lihua Li Huang ,  Martin Jay Seamons ,  Soovo Sen ,  Reza Arghavani ,  Michael Chiu Kwan

发明人： Kee Bum Jung ,  Dale R. Du Bois ,  Lun Tsuei ,  Lihua Li Huang ,  Martin Jay Seamons ,  Soovo Sen ,  Reza Arghavani ,  Michael Chiu Kwan

IPC分类号： H01L21/318

CPC分类号： C23C16/45574 ,  C23C16/345 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/50 ,  H01J37/3244 ,  H01L21/0217 ,  H01L21/3185

摘要： A dual channel gas distributor can simultaneously distribute plasma species of an first process gas and a non-plasma second process gas into a process zone of a substrate processing chamber. The gas distributor has a localized plasma box with a first inlet to receive a first process gas, and opposing top and bottom plates that are capable of being electrically biased relative to one another to define a localized plasma zone in which a plasma of the first process gas can be formed. The top plate has a plurality of spaced apart gas spreading holes to spread the first process gas across the localized plasma zone, and the bottom plate has a plurality of first outlets to distribute plasma species of the plasma of the first process gas into the process zone. A plasma isolated gas feed has a second inlet to receive the second process gas and a plurality of second outlets to pass the second process gas into the process zone. A plasma isolator is between the second inlet and second outlets to prevent formation of a plasma of the second process gas in the plasma isolated gas feed.

摘要翻译： 双通道气体分配器可以将第一工艺气体和非等离子体第二工艺气体的等离子体种类同时分配到衬底处理室的工艺区域中。 气体分配器具有局部等离子体箱，其具有第一入口以接收第一处理气体，以及相对的顶板和底板，其能够相对于彼此电偏置以限定局部等离子体区，其中第一工艺的等离子体 可以形成气体。 顶板具有多个间隔开的气体扩散孔，以将第一处理气体扩散通过局部等离子体区域，并且底板具有多个第一出口，用于将第一处理气体的等离子体的等离子体物质分配到处理区 。 等离子体隔离气体进料具有用于接收第二处理气体的第二入口和多个第二出口以将第二处理气体通入处理区。 等离子体隔离器位于第二入口和第二出口之间，以防止在等离子体隔离气体进料中形成第二工艺气体的等离子体。