公开(公告)号：US20130040465A1

公开(公告)日：2013-02-14

申请号：US13381005

申请日：2011-08-10

申请人： Lingkuan Meng ,  Huaxiang Yin

发明人： Lingkuan Meng ,  Huaxiang Yin

IPC分类号： H01L21/3065

CPC分类号： H01L21/31055 ,  H01L21/76801 ,  H01L29/78

摘要： The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.

摘要翻译： 本发明公开了一种用于在层间电介质（ILD）的位置 - 接近界​​面处的平坦化的回蚀方法，包括：通过化学气相沉积或氧化方法在晶片的表面上沉积或生长厚SiO 2层; 旋涂一层SOG，然后进行热处理以获得相对均匀的堆叠结构; 使用等离子体蚀刻对SOG进行回蚀，并且在接近SiO 2的位置 - 接近界​​面时停止; 在靠近界面的位置处对剩余的SOG / SiO 2结构进行等离子体回蚀，直到达到期望的厚度。 由于在位置 - 接近界​​面处进行两步蚀刻，因此获得了非常好的ILD平滑表面。 也就是说，ILD的平面和整洁的表面不仅在中心区域中获得，而且在晶片的边缘处获得。

公开(公告)号：US08728948B2

公开(公告)日：2014-05-20

申请号：US13700775

申请日：2012-09-05

申请人： Lingkuan Meng

发明人： Lingkuan Meng

IPC分类号： H01L21/302

CPC分类号： H01L29/66477 ,  H01L21/31116 ,  H01L22/26 ,  H01L29/66545 ,  H01L29/6656

摘要： A method of manufacturing a semiconductor device is disclosed. The method may comprise: forming a gate stack on a substrate; depositing a first dielectric layer and a second dielectric layer sequentially on the substrate and the gate stack; and etching the second dielectric layer and the first dielectric layer sequentially with an etching gas containing helium to form a second spacer and a first spacer, respectively. According to the method disclosed herein, a dual-layer complex spacer configuration is achieved, and two etching operations where the etching gas comprises the helium gas are performed. As a result, it is possible to reduce damages to the substrate and also to reduce the process complexity. Further, it is possible to optimize a threshold voltage, effectively reduce an EOT, and enhance a gate control capability and a driving current.

摘要翻译： 公开了制造半导体器件的方法。 该方法可以包括：在衬底上形成栅叠层; 在衬底和栅极堆叠上依次沉积第一介电层和第二介质层; 以及分别用包含氦的蚀刻气体依次蚀刻所述第二介电层和所述第一介电层，以分别形成第二间隔物和第一间隔物。 根据本文公开的方法，实现双层复合间隔物配置，并且执行蚀刻气体包括氦气的两种蚀刻操作。 结果，可以减少对基板的损伤，并且还可以降低工艺的复杂性。 此外，可以优化阈值电压，有效地减少EOT，并且增强门控制能力和驱动电流。

公开(公告)号：US20120282756A1

公开(公告)日：2012-11-08

申请号：US13505993

申请日：2012-01-18

申请人： Lingkuan Meng

发明人： Lingkuan Meng

IPC分类号： H01L21/762

CPC分类号： H01L21/02274 ,  C23C16/045 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/31116 ,  H01L21/76224

摘要： The present invention relates to a thin film filling method, including: feeding reactive gases including a silicon-containing gas, an oxygen-containing gas, an inert gas and a fluent gas into a reaction chamber; forming a first deposited thin film in the trench or gap through HDP CVD; feeding an etching gas and the fluent gas without feeding said silicon-containing gas and oxygen-containing gas, to sputter the surface of the first deposited thin film; feeding said silicon-containing gas and oxygen-containing gas without feeding said etching gas, so that a second deposited thin film is formed on the surface of the sputtered first deposited thin film; feeding said etching gas and fluent gas without feeding said silicon-containing gas and oxygen-containing gas, to sputtering the surface of said second deposited thin film; repeating the last two steps; feeding the silicon-containing gas and oxygen-containing gas without feeding the etching gas to form a plasmas of low pressure and high density, so that a third deposited thin film, which completely fills said trench or gap, is formed on the surface of the sputtered second deposited thin film.

摘要翻译： 本发明涉及一种薄膜填充方法，包括：将含有含硅气体，含氧气体，惰性气体和流动气体的反应性气体进料到反应室中; 通过HDP CVD在沟槽或间隙中形成第一沉积薄膜; 在不进料所述含硅气体和含氧气体的情况下进料蚀刻气体和流动气体，以溅射第一沉积薄膜的表面; 在不进料所述蚀刻气体的情况下进料所述含硅气体和含氧气体，从而在溅射的第一沉积薄膜的表面上形成第二沉积薄膜; 在不进料所述含硅气体和含氧气体的情况下进料所述蚀刻气体和流动气体，以溅射所述第二沉积薄膜的表面; 重复最后两个步骤; 在不进料蚀刻气体的情况下进料含硅气体和含氧气体以形成低压和高密度的等离子体，从而在其表面上形成完全填充所述沟槽或间隙的第三沉积薄膜 溅射第二沉积薄膜。

公开(公告)号：US20120164838A1

公开(公告)日：2012-06-28

申请号：US13147044

申请日：2011-02-17

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC分类号： H01L21/263

CPC分类号： H01L21/76819 ,  H01L21/31055 ,  H01L21/31116

摘要： The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.

摘要翻译： 本申请公开提供了一种用于平坦化层间电介质层的方法，包括以下步骤：提供包括至少一个牺牲层和在半导体衬底和第一栅极叠层下的牺牲层下方的至少一个绝缘层的多层结构，执行 多层结构中的第一RIE，其中反应室压力被控制为使得晶片中心处的至少一个牺牲层的部分的蚀刻速率高于晶片的边缘处的蚀刻速率 ，以获得凹蚀刻轮廓; 在所述多层结构上执行第二RIE以完全去除所述牺牲层和所述绝缘层的一部分，从而获得具有用作层间介质层的平坦表面的所述绝缘层。 平坦化处理可以代替用于提供具有平坦表面的层间介电层的CMP工艺，其实现了晶片的相对较大的可用面积。

公开(公告)号：US20120164808A1

公开(公告)日：2012-06-28

申请号：US13129419

申请日：2011-02-17

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76819 ,  H01L29/66545 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。

公开(公告)号：US20140199846A1

公开(公告)日：2014-07-17

申请号：US13883834

申请日：2012-09-05

申请人： Lingkuan Meng

发明人： Lingkuan Meng

IPC分类号： H01L21/768

CPC分类号： H01L21/76816 ,  H01L21/76831

摘要： A method of manufacturing a semiconductor device is disclosed. The method may comprise: etching a plurality of first openings in an interlayer dielectric layer on a substrate; forming an opening modifying layer in the plurality of first openings; and etching the opening modifying layer until the substrate is exposed, resulting in a plurality of second openings, wherein the second openings have a depth-to-width ratio greater than that of the first openings. In this way, a deep hole with a relatively large dimension can be formed in silicon oxide by conventional photolithography processes. After that, a film of silicon nitride can be deposited into the hole to achieve a desired CD, and then etched with the fluorocarbon gas(es) to implement an arrangement with a relatively great depth-to-width ratio.

摘要翻译： 公开了制造半导体器件的方法。 该方法可以包括：蚀刻衬底上的层间电介质层中的多个第一开口; 在所述多个第一开口中形成开口改性层; 并且蚀刻所述开口改性层直到所述基板被暴露，从而产生多个第二开口，其中所述第二开口具有大于所述第一开口的深宽比。 以这种方式，通过常规的光刻工艺可以在氧化硅中形成具有较大尺寸的深孔。 此后，可以将氮化硅膜沉积到孔中以获得所需的CD，然后用碳氟化合物气体蚀刻以实现相对较大的深度 - 宽度比的布置。

公开(公告)号：US08703617B2

公开(公告)日：2014-04-22

申请号：US13147044

申请日：2011-02-17

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC分类号： H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

CPC分类号： H01L21/76819 ,  H01L21/31055 ,  H01L21/31116

摘要： The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.

摘要翻译： 本申请公开提供了一种用于平坦化层间电介质层的方法，包括以下步骤：提供包括至少一个牺牲层和在半导体衬底和第一栅极叠层下的牺牲层下方的至少一个绝缘层的多层结构，执行 多层结构中的第一RIE，其中反应室压力被控制为使得晶片中心处的至少一个牺牲层的部分的蚀刻速率高于晶片的边缘处的蚀刻速率 ，以获得凹蚀刻轮廓; 在所述多层结构上执行第二RIE以完全去除所述牺牲层和所述绝缘层的一部分，从而获得具有用作层间介质层的平坦表面的所述绝缘层。 平坦化处理可以代替用于提供具有平坦表面的层间介电层的CMP工艺，其实现了晶片的相对较大的可用面积。

公开(公告)号：US08664119B2

公开(公告)日：2014-03-04

申请号：US13497526

申请日：2011-11-28

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Dapeng Chen

IPC分类号： H01L21/311 ,  H01L21/461

CPC分类号： H01L21/31053 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823807 ,  H01L29/66545

摘要： A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.

摘要翻译： 一种半导体器件制造方法，包括：提供半导体衬底，在所述半导体衬底上设置栅极导体层以及位于所述栅极导体层两侧的源极区域和漏极区域，在所述半导体衬底上形成蚀刻停止层 在蚀刻停止层上形成LTO层，化学机械抛光LTO层，在抛光的LTO层上形成SOG层，形成前金属绝缘层的蚀刻停止层，LTO层和SOG层，背面蚀刻SOG层 和前金属绝缘层的蚀刻停止层，以露出栅极导体层，以及去除栅极导体层。

公开(公告)号：US08324061B2

公开(公告)日：2012-12-04

申请号：US13129419

申请日：2011-02-17

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76819 ,  H01L29/66545 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。

公开(公告)号：US08883584B2

公开(公告)日：2014-11-11

申请号：US13700808

申请日：2012-09-05

申请人： Lingkuan Meng

发明人： Lingkuan Meng

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/66545 ,  H01L21/31116

摘要： A method of manufacturing a semiconductor device is disclosed. The method may comprise: forming a gate stack on a substrate; depositing a dielectric layer on the substrate and the gate stack; performing a main etching operation on the dielectric layer to form a spacer, with a remainder of the dielectric layer left on the substrate; and performing an over etching operation to remove the remainder of the dielectric layer. According to the method disclosed herein, two etching operations where an etching gas comprises a helium gas are performed, without forming an etching stop layer of silicon oxide. As a result, it is possible to reduce damages to the substrate and also to reduce the process complexity. Further, it is possible to optimize a threshold voltage, effectively reduce an EOT, and enhance a gate control capability and a driving current.

摘要翻译： 公开了制造半导体器件的方法。 该方法可以包括：在衬底上形成栅叠层; 在基板和栅极堆叠上沉积介电层; 在介电层上进行主蚀刻操作以形成间隔物，剩余的电介质层留在基片上; 并执行过蚀刻操作以去除电介质层的其余部分。 根据本文公开的方法，执行蚀刻气体包括氦气的两种蚀刻操作，而不形成氧化硅的蚀刻停止层。 结果，可以减少对基板的损伤，并且还可以降低工艺的复杂性。 此外，可以优化阈值电压，有效地减少EOT，并且增强门控制能力和驱动电流。