Stacked die semiconductor package and method of assembly
    1.
    发明申请
    Stacked die semiconductor package and method of assembly 有权
    堆叠半导体封装和组装方法

    公开(公告)号:US20090004777A1

    公开(公告)日:2009-01-01

    申请号:US12124880

    申请日:2008-05-21

    IPC分类号: H01L21/00

    摘要: A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.

    摘要翻译: 一种制造多个堆叠管芯半导体封装的方法,包括:将第二硅晶片连接到第一硅晶片,其中所述第二硅晶片具有多个开口; 将第三硅晶片附接到所述第二硅晶片,其中所述第三硅晶片具有多个开放通孔,并且所述第二和第三硅晶片的所述开放通孔彼此对准; 蚀刻从对准的开放通孔连接晶片的接合材料; 用导体填充对齐的开放通孔; 在对齐的开放通孔的开口端形成导电凸块; 背面研磨第一个硅晶片; 将堆叠的半导体管芯彼此分离; 将堆叠的半导体管芯的凸起端附接到基板上; 封装堆叠的半导体管芯和衬底; 并分离封装的组件。

    Automatic browsing path generation to present image areas with high attention value as a function of space and time
    3.
    发明授权
    Automatic browsing path generation to present image areas with high attention value as a function of space and time 有权
    自动浏览路径生成,以高度的注意力来呈现作为空间和时间的函数的图像区域

    公开(公告)号:US07471827B2

    公开(公告)日:2008-12-30

    申请号:US10688471

    申请日:2003-10-16

    IPC分类号: G06K9/34

    CPC分类号: G06F17/30905

    摘要: Systems and methods for automatic generation of a browsing path across image content to present areas with high attention value are described. In particular, an image is modeled via multiple visual attentions to create a respective set of attention objects for each modeled attention. The attention objects and their respective attributes are analyzed to generate a browsing path to select ones of the attention objects. The browsing path is generated to optimize the rate of information gain from the attention objects as a function of information unit cost in terms of time constraints associated with multiple image browsing modes.

    摘要翻译: 描述了跨越图像内容自动生成浏览路径以呈现具有高注意力值的区域的系统和方法。 特别地,通过多个视觉注意来建模图像,以为每个建模的注意创建相应的一组关注对象。 分析注意对象及其各自的属性,生成浏览路径以选择注意对象。 生成浏览路径以根据与多个图像浏览模式相关联的时间约束来优化来自注意对象的信息增益的速率作为信息单元成本的函数。

    Automatic browsing path generation to present image areas with high attention value as a function of space and time
    5.
    发明申请
    Automatic browsing path generation to present image areas with high attention value as a function of space and time 有权
    自动浏览路径生成,以高度的注意力来呈现作为空间和时间的函数的图像区域

    公开(公告)号:US20050084136A1

    公开(公告)日:2005-04-21

    申请号:US10688471

    申请日:2003-10-16

    IPC分类号: G06F17/30 G06K9/00

    CPC分类号: G06F17/30905

    摘要: Systems and methods for automatic generation of a browsing path across image content to present areas with high attention value are described. In particular, an image is modeled via multiple visual attentions to create a respective set of attention objects for each modeled attention. The attention objects and their respective attributes are analyzed to generate a browsing path to select ones of the attention objects. The browsing path is generated to optimize the rate of information gain from the attention objects as a function of information unit cost in terms of time constraints associated with multiple image browsing modes.

    摘要翻译: 描述了跨越图像内容自动生成浏览路径以呈现具有高注意力值的区域的系统和方法。 特别地,通过多个视觉注意来建模图像,以为每个建模的注意创建相应的一组关注对象。 分析注意对象及其各自的属性,生成浏览路径以选择注意对象。 生成浏览路径以根据与多个图像浏览模式相关联的时间约束来优化来自注意对象的信息增益的速率作为信息单元成本的函数。

    Stacked die semiconductor package and method of assembly
    7.
    发明授权
    Stacked die semiconductor package and method of assembly 有权
    堆叠半导体封装和组装方法

    公开(公告)号:US07883938B2

    公开(公告)日:2011-02-08

    申请号:US12124880

    申请日:2008-05-21

    IPC分类号: H01L21/00

    摘要: A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.

    摘要翻译: 一种制造多个堆叠管芯半导体封装的方法,包括:将第二硅晶片连接到第一硅晶片,其中所述第二硅晶片具有多个开口; 将第三硅晶片附接到所述第二硅晶片,其中所述第三硅晶片具有多个开放通孔,并且所述第二和第三硅晶片的所述开放通孔彼此对准; 蚀刻从对准的开放通孔连接晶片的接合材料; 用导体填充对齐的开放通孔; 在对齐的开放通孔的开口端形成导电凸块; 背面研磨第一个硅晶片; 将堆叠的半导体管芯彼此分离; 将堆叠的半导体管芯的凸起端附接到基板上; 封装堆叠的半导体管芯和衬底; 并分离封装的组件。