公开(公告)号：US08836306B2

公开(公告)日：2014-09-16

申请号：US13618652

申请日：2012-09-14

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

IPC: H02M3/157 ,  H02M3/158

CPC classification number: H02M3/1584 ,  H02M2003/1586 ,  Y10T307/582

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Abstract translation: 用于向负载递送电力的集成电路装置包括控制器电路，级联电路和电力输送电路。 控制器电路产生多个控制信号。 级联电路从控制器电路接收控制信号，并将控制信号依次输出到级联总线上。 功率传递电路响应于控制信号之一，接收来自控制器电路的控制信号并将一定量的电流传送到负载。

公开(公告)号：US20100321971A1

公开(公告)日：2010-12-23

申请号：US12873183

申请日：2010-08-31

Applicant: Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

Inventor： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Abstract translation: 内容可寻址存储器（CAM）设备包括多个CAM行，多个排序逻辑电路和可编程互连结构。 每个CAM行包括多个CAM单元，以在匹配线上生成匹配信号并且包括使能输入。 每个排序逻辑电路包括输入和输出，并且被配置为对来自CAM行的匹配信号的序列进行计数。 可编程互连结构选择性地将任何CAM行的匹配线连接到任何排序逻辑电路的输入，并且将任何排序逻辑电路的输出选择性地连接到任何CAM行的使能输入。

公开(公告)号：US20100321970A1

公开(公告)日：2010-12-23

申请号：US12873122

申请日：2010-08-31

Applicant: Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

Inventor： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

IPC: G11C15/00 ,  G11C7/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.

Abstract translation: 内容可寻址存储器（CAM）装置包括CAM阵列，可编程互连结构和优先编码器。 CAM阵列包括多个CAM行，每行包括用于存储数据字并耦合到指示CAM行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行和多个CAM行，每行包括用于存储数据字并耦合到指示行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行，并且被配置为将任何数目N个所选择的CAM行逻辑地连接在一起，以形成横跨N行的数据字链，而不管所选择的CAM行是否是连续的。

公开(公告)号：US08631195B1

公开(公告)日：2014-01-14

申请号：US12132053

申请日：2008-06-03

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  Mark Birman

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  Mark Birman

IPC: G06F12/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A search system for detecting whether one or more overlapping sequences of input characters match a regular expression including a prefix string preceding an intermediate expression having a quantified number m of characters belonging to a specified character class is disclosed. The search system includes a CAM array for storing the regular expression, a shift register for counting sequences of input characters that match the character class, and a control circuit that enables the shift register in response to a prefix match and increments the shift register in response to character class matches.

Abstract translation: 公开了一种用于检测输入字符的一个或多个重叠序列与包含具有属于指定字符类的字符的量化数字m的中间表达式之前的前缀字符串的正则表达式相匹配的搜索系统。 搜索系统包括用于存储正则表达式的CAM阵列，用于对与字符类匹配的输入字符的序列进行计数的移位寄存器以及响应于前缀匹配使移位寄存器能够响应的递增移位寄存器的控制电路 到角色类比赛。

公开(公告)号：US08023300B1

公开(公告)日：2011-09-20

申请号：US12818555

申请日：2010-06-18

Applicant: Varadarajan Srinivasan ,  Chetan Deshpande ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Venkat Rajendher Reddy Gaddam

Inventor： Varadarajan Srinivasan ,  Chetan Deshpande ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Venkat Rajendher Reddy Gaddam

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: Present embodiments allow a search engine to quickly save and restore state information to and from an external state memory when switching between multiple data flows by transferring the state information between the search engine and the external state memory in a parallel manner. More specifically, for CAM-based search engines configured according to present embodiments, the CAM array includes state information gating circuits that selectively allow state information stored in the CAM array's match latches to be transposed onto the array's bit lines and then read from the array using the array's sense amplifiers.

Abstract translation: 当前实施例允许搜索引擎通过以并行方式在搜索引擎和外部状态存储器之间传送状态信息来在多个数据流之间切换时，将状态信息快速地保存到外部状态存储器和从外部状态存储器恢复状态信息。 更具体地，对于根据本实施例配置的基于CAM的搜索引擎，CAM阵列包括状态信息门控电路，其选择性地允许存储在CAM阵列的匹配锁存器中的状态信息被转置到阵列的位线上，然后使用 阵列的读出放大器。

公开(公告)号：US07643353B1

公开(公告)日：2010-01-05

申请号：US12131992

申请日：2008-06-03

Applicant: Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

Inventor： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

IPC: G11C7/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and is configured to selectively route the match results from a first CAM row as an input match signal to any number of arbitrarily selected CAM rows at the same time.

Abstract translation: 内容可寻址存储器（CAM）装置包括CAM阵列，可编程互连结构和优先编码器。 CAM阵列包括多个CAM行，每行包括用于存储数据字并耦合到指示CAM行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行，并且被配置为选择性地将来自第一CAM行的匹配结果作为输入匹配信号同时路由到任意数量的任意选择的CAM行。

公开(公告)号：US08901909B2

公开(公告)日：2014-12-02

申请号：US13618617

申请日：2012-09-14

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

IPC: H02M3/157 ,  H02M3/158

CPC classification number: H02M3/1584 ,  H02M2003/1586 ,  Y10T307/582

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

公开(公告)号：US20130009479A1

公开(公告)日：2013-01-10

申请号：US13618617

申请日：2012-09-14

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

IPC: H02J1/10

CPC classification number: H02M3/1584 ,  H02M2003/1586 ,  Y10T307/582

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

公开(公告)号：US08051085B1

公开(公告)日：2011-11-01

申请号：US12505372

申请日：2009-07-17

Applicant: Maheshwaran Srinivasan ,  Alexey Starovoytov

Inventor： Maheshwaran Srinivasan ,  Alexey Starovoytov

IPC: G06F7/00

CPC classification number: H04L63/1416 ,  H04L63/0245

Abstract: A method and apparatus are disclosed for determining the lengths of one or more substrings of an input string that matches a regular expression (regex) The input string is searched for the regex using an non-deterministic finite automaton (NFA), and upon detecting a match state a selected portion of the input string is marked as a match string. The NFA is inverted to create a reverse NFA that embodies the inverse of the regex. For some embodiments, the reverse NFA is created by inverting the NFA such that the match state of the NFA becomes the initial state of the reverse NFA, the initial state of the NFA becomes the match state of the reverse NFA, and the goto transitions of the NFA are inverted to form corresponding goto transitions in the reverse NFA. The match string is reversed and searched for the inverted regex using the reverse NFA, and a counter is incremented for each character processed during the reverse search operation. The current value of the counter each time the match state in the reverse NFA is reached indicates the character length of a corresponding substring that matches the regex.

Abstract translation: 公开了用于确定与正则表达式（正则表达式）匹配的输入字符串的一个或多个子串的长度的方法和装置。使用非确定性有限自动机（NFA）来搜索正则表达式的输入字符串，并且在检测到 匹配状态输入字符串的选定部分被标记为匹配字符串。 NFA被反转以产生体现正则表达式的倒数的反向NFA。 对于一些实施例，通过颠倒NFA来创建反向NFA，使得NFA的匹配状态变为反向NFA的初始状态，NFA的初始状态变为反向NFA的匹配状态，并且转向 反向NFA反向NFA形成相应的goto转变。 匹配字符串反向，使用反向NFA搜索倒置的正则表达式，并且在反向搜索操作期间为每个处理的字符递增计数器。 每次达到反向NFA的匹配状态时，计数器的当前值表示与正则表达式匹配的相应子字符串的字符长度。

公开(公告)号：US08023301B1

公开(公告)日：2011-09-20

申请号：US12899171

申请日：2010-10-06

Applicant: Varadarajan Srinivasan ,  Maheshwaran Srinivasan ,  Chetan Deshpande ,  Sandeep Khanna ,  Venkat Rajendher Reddy Gaddam

Inventor： Varadarajan Srinivasan ,  Maheshwaran Srinivasan ,  Chetan Deshpande ,  Sandeep Khanna ,  Venkat Rajendher Reddy Gaddam

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: Present embodiments allow a search engine to quickly save and restore state information to and from an external state memory when switching between multiple data flows by transferring the state information between the search engine and the external state memory in a parallel manner. More specifically, for CAM-based search engines configured according to present embodiments, the CAM array includes state information gating circuits that selectively allow state information stored in the CAM array's match latches to be transposed onto the array's bit lines and then read from the array using the array's sense amplifiers.

Abstract translation: 当前实施例允许搜索引擎通过以并行方式在搜索引擎和外部状态存储器之间传送状态信息来在多个数据流之间切换时，将状态信息快速地保存到外部状态存储器和从外部状态存储器恢复状态信息。 更具体地，对于根据本实施例配置的基于CAM的搜索引擎，CAM阵列包括状态信息门控电路，其选择性地允许存储在CAM阵列的匹配锁存器中的状态信息被转置到阵列的位线上，然后使用 阵列的读出放大器。