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公开(公告)号：US08161350B2
公开(公告)日：2012-04-17
申请号：US11988252
申请日：2006-06-30
IPC分类号： H03M13/00
CPC分类号： H03M13/1194 , H03M13/1105 , H03M13/116 , H03M13/118 , H03M13/1185 , H03M13/2906
摘要： A communication method and a communication system including a first entity (3) including an information source (9) and a coder device (11) connected by a channel (7) transmitting data to a second entity (5) including a decoder device (13), the coder device (11) coding a data sequence sent by the information source (9) to form a set of code words from a parity check matrix including two matrix areas, each matrix area including a processing matrix, a connecting matrix including only one “1” per column and only one “1” per row, and a triangular matrix, and the decoder device (13) decoding a coded reception signal that is received by the second entity and is derived from the set of code words constructed in accordance with said parity check matrix.
摘要翻译： 一种通信方法和通信系统，包括第一实体（3），包括信息源（9）和编码器装置（11），通过信道（7）连接到包括解码器装置（13）的第二实体（5）的信道 ），编码器装置（11）对由信息源（9）发送的数据序列进行编码，以从包括两个矩阵区域的奇偶校验矩阵形成一组码字，每个矩阵区域包括处理矩阵，仅包括连接矩阵 每列一个“1”，每行仅一个“1”，三角矩阵，解码器装置（13）对由第二实体接收的编码的接收信号进行解码，并从构成的代码字集合 根据所述奇偶校验矩阵。
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公开(公告)号：US08214723B2
公开(公告)日：2012-07-03
申请号：US12223109
申请日：2007-01-18
IPC分类号： H03M13/00
CPC分类号： H03M13/2972 , H03M13/1194 , H03M13/2771 , H03M13/2978 , H03M13/6566
摘要： A method of low latency encoding of an input bit sequence (S0) to yield an encoded bit sequence (S), and a corresponding decoding method, said encoding method including: a first encoding step (E1) applied to bits of the input bit sequence (S0), using a first code; an interleaving step (E3) in which an interleaver interleaves the bits obtained from said first code; and a parity, second encoding step (E4) applied to the bits obtained from said interleaver, using a second code, to generate said encoded bit sequence (S). The parity, second encoding step (E4) starts after a predetermined number Δ of bits have been interleaved, said predetermined number Δ of bits ranging between a first lower number Δi of bits depending on one or more parameters of said interleaving step (E3) and a first higher number Δs of bits corresponding to the total number of bits to be processed during said interleaving step (E3).
摘要翻译： 一种输入比特序列（S0）的低延迟编码以产生编码比特序列（S）的方法和相应的解码方法，所述编码方法包括：第一编码步骤（E1），其应用于输入比特序列 （S0），使用第一代码; 交织步骤（E3），其中交织器交织从所述第一码获得的比特; 以及使用第二代码应用于从所述交织器获得的比特的奇偶校验第二编码步骤（E4），以生成所述编码比特序列（S）。 奇偶校验第二编码步骤（E4）在预定数量＆Dgr之后开始; 的位已被交织，所述预定数量＆Dgr; 根据所述交织步骤（E3）的一个或多个参数和与在所述交织步骤期间要处理的总位数相对应的比特的第一较高数目＆Dgr比特，位于第一较低数字＆amp; （E3）。
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公开(公告)号：US20100287437A1
公开(公告)日：2010-11-11
申请号：US12223109
申请日：2007-01-18
CPC分类号： H03M13/2972 , H03M13/1194 , H03M13/2771 , H03M13/2978 , H03M13/6566
摘要： A method of low latency encoding of an input bit sequence (S0) to yield an encoded bit sequence (S), and a corresponding decoding method, said encoding method including: a first encoding step (E1) applied to bits of the input bit sequence (S0), using a first code; an interleaving step (E3) in which an interleaver interleaves the bits obtained from said first code; and a parity, second encoding step (E4) applied to the bits obtained from said interleaver, using a second code, to generate said encoded bit sequence (S). The parity, second encoding step (E4) starts after a predetermined number Δ of bits have been interleaved, said predetermined number Δ of bits ranging between a first lower number Δi of bits depending on one or more parameters of said interleaving step (E3) and a first higher number Δs of bits corresponding to the total number of bits to be processed during said interleaving step (E3).
摘要翻译： 一种输入比特序列（S0）的低延迟编码以产生编码比特序列（S）的方法和相应的解码方法，所述编码方法包括：第一编码步骤（E1），其应用于输入比特序列 （S0），使用第一代码; 交织步骤（E3），其中交织器交织从所述第一码获得的比特; 以及使用第二代码应用于从所述交织器获得的比特的奇偶校验第二编码步骤（E4），以生成所述编码比特序列（S）。 奇偶校验第二编码步骤（E4）在预定数量＆Dgr之后开始; 的位已被交织，所述预定数量＆Dgr; 根据所述交织步骤（E3）的一个或多个参数和与在所述交织步骤期间要处理的总位数相对应的比特的第一较高数目＆Dgr比特，位于第一较低数字＆amp; （E3）。
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