公开(公告)号：US6091660A

公开(公告)日：2000-07-18

申请号：US376468

申请日：1999-08-18

申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

IPC分类号： G11C11/401 ,  G11C8/00 ,  G11C8/12 ,  G11C11/407

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

摘要翻译： 安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。 分别提供用于分别执行+1或-1算术运算的算术电路，以便对应于相应的存储器垫并且以级联形式电连接。 初始级算术电路的输入端被提供地址设定固定地址信号。 提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。 与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。 基于所得到的一致信号来选择相应的存储器垫。

公开(公告)号：US5978305A

公开(公告)日：1999-11-02

申请号：US165194

申请日：1998-10-02

申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

IPC分类号： G11C11/401 ,  G11C8/00 ,  G11C8/12 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

公开(公告)号：US06314044B1

公开(公告)日：2001-11-06

申请号：US09594840

申请日：2000-06-15

申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

IPC分类号： G11C800

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

摘要翻译： 安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。 分别提供用于分别执行+1或-1运算的算术电路，以对应于相应的存储器垫并且以级联形式电连接。 初始级算术电路的输入端被提供地址设定固定地址信号。 提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。 与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。 基于所得到的一致信号来选择相应的存储器垫。

公开(公告)号：US06301184B1

公开(公告)日：2001-10-09

申请号：US09480695

申请日：2000-01-11

申请人： Toshio Sasaki ,  Yoshihiko Yasu ,  Kazumasa Yanagisawa ,  Yuji Tanaka ,  Toshiaki Takahira ,  Yasuto Igarashi ,  Mariko Ohtsuka ,  Yasunobu Aoki

发明人： Toshio Sasaki ,  Yoshihiko Yasu ,  Kazumasa Yanagisawa ,  Yuji Tanaka ,  Toshiaki Takahira ,  Yasuto Igarashi ,  Mariko Ohtsuka ,  Yasunobu Aoki

IPC分类号： G11C800

CPC分类号： G11C11/4074 ,  G11C7/1045

摘要： A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.

摘要翻译： 将DRAM模块应用于具有用于抑制其整体操作的待机模式的系统LSI和至少允许DRAM模块操作但抑制其它电路的操作的操作待机模式。 将上述模式以及衬底偏置控制技术应用于在低电压下工作的CMOS系统LSI。 控制系统LSI以保持或不保存数据，使得能够安装大容量的存储器并消耗足够的电力量。