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    LOCOS isolation for fully-depleted SOI devices
    4.
    发明授权
    LOCOS isolation for fully-depleted SOI devices 失效
    用于完全耗尽的SOI器件的LOCOS隔离

    公开(公告)号：US07510927B2

    公开(公告)日：2009-03-31

    申请号：US10330842

    申请日：2002-12-26

    申请人： Mark Bohr ,  Julie Tsai

    发明人： Mark Bohr ,  Julie Tsai

    IPC分类号： H01L21/84

    CPC分类号： H01L21/76264

    摘要： The present invention discloses a method including: providing a substrate; forming a buried oxide layer over the substrate; forming a thin silicon body layer over the buried oxide layer, the thin silicon body layer having a thickness of 3-40 nanometers; forming a pad oxide layer over the thin silicon body layer; forming a silicon nitride layer over the pad oxide layer; forming a photoresist over the silicon nitride layer; forming an opening in the photoresist; removing the silicon nitride layer in the opening; partially or completely removing the pad oxide layer in the opening; removing the photoresist over the silicon nitride layer; forming a field oxide layer from the thin silicon body layer in the opening; removing the silicon nitride layer over the pad oxide layer; and removing the pad oxide layer over the thin silicon body layer.The present invention also discloses a structure including: a substrate; a buried oxide layer located over the substrate; a thin silicon body layer located over the buried oxide layer, the thin silicon body layer including active areas separated by isolation regions, the isolation regions having a modified bird's beak length that is 30-60% of a thickness of the thin silicon body layer; and a fully-depleted device located in each of the active regions.

    摘要翻译： 本发明公开了一种方法，包括：提供基板; 在衬底上形成掩埋氧化层; 在所述掩埋氧化物层上形成薄的硅体层，所述薄硅体层的厚度为3-40纳米; 在所述薄硅体层上形成衬垫氧化物层; 在所述焊盘氧化物层上形成氮化硅层; 在氮化硅层上形成光致抗蚀剂; 在光致抗蚀剂中形成开口; 去除开口中的氮化硅层; 部分地或完全地去除开口中的垫氧化物层; 去除氮化硅层上的光致抗蚀剂; 从所述开口中的所述薄硅体层形成场氧化物层; 去除所述衬垫氧化物层上的所述氮化硅层; 以及去除所述薄硅体层上的所述衬垫氧化物层。 本发明还公开了一种结构，包括：基板; 位于衬底上方的掩埋氧化物层; 位于所述掩埋氧化物层上方的薄硅体层，所述薄硅体层包括由隔离区隔开的有效区域，所述隔离区域具有所述薄硅体层的厚度的30-60％的改进的鸟嘴长度; 以及位于每个活动区域中的完全耗尽的装置。

    MICROCIRCUIT FABRICATION AND INTERCONNECTION
    5.
    发明申请
    MICROCIRCUIT FABRICATION AND INTERCONNECTION 有权
    微型制造和互连

    公开(公告)号：US20080119016A1

    公开(公告)日：2008-05-22

    申请号：US12023867

    申请日：2008-01-31

    申请人： Valery Dubin ,  Mark Bohr

    发明人： Valery Dubin ,  Mark Bohr

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L29/76 ,  B82Y10/00 ,  H01L21/768 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53276 ,  H01L29/66439 ,  H01L29/7613 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

    摘要翻译： 根据本发明的方法的实施例提供了三维碳纳米管（CNT）集成电路，其包括由电介质层分离的CNT阵列层，其中形成有介电层内的导电迹线以电连接各个CNT。 制造三维碳纳米管FET集成电路的方法包括将碳纳米管选择性沉积到选择性地形成在电介质层的开口底部的导电层上的催化剂上。 电介质层中的开口使用合适的技术形成，例如但不限于电介质蚀刻，以及形成包括间隔物的环形栅电极，其提供用于沉积自对准碳纳米管半导体通道的开口。

    Microcircuit fabrication and interconnection
    6.
    发明授权
    Microcircuit fabrication and interconnection 有权
    微电路制造和互连

    公开(公告)号：US07348675B2

    公开(公告)日：2008-03-25

    申请号：US11048231

    申请日：2005-02-01

    申请人： Valery M. Dubin ,  Mark Bohr

    发明人： Valery M. Dubin ,  Mark Bohr

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

    CPC分类号： H01L29/76 ,  B82Y10/00 ,  H01L21/768 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53276 ,  H01L29/66439 ,  H01L29/7613 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

    摘要翻译： 根据本发明的方法的实施例提供了三维碳纳米管（CNT）集成电路，其包括由电介质层分离的CNT阵列层，其中形成有介电层内的导电迹线以电连接各个CNT。 制造三维碳纳米管FET集成电路的方法包括将碳纳米管选择性沉积到选择性地形成在电介质层的开口底部的导电层上的催化剂上。 电介质层中的开口使用合适的技术形成，例如但不限于电介质蚀刻，以及形成包括间隔物的环形栅电极，其提供用于沉积自对准碳纳米管半导体通道的开口。

    Copper-filled trench contact for transistor performance improvement
    7.
    发明申请
    Copper-filled trench contact for transistor performance improvement 有权
    用于晶体管性能改善的铜填充沟槽接触

    公开(公告)号：US20070273042A1

    公开(公告)日：2007-11-29

    申请号：US11396201

    申请日：2006-05-23

    申请人： Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

    发明人： Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

    IPC分类号： H01L23/48

    CPC分类号： H01L29/41725 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

    摘要翻译： 制造半导体器件的第一接触的方法，其基本上包括提供形成在衬底上的半导体器件。 基板还包括导电表面。 介电层形成在衬底上并具有暴露导电表面的开口。 开口延伸半导体器件的整个长度，从设备的整个长度的一部分延伸到器件的相邻的场上，或其组合。 在开口内形成阻挡层。 含铜材料填充开口以形成与半导体器件的第一接触。