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    CMOS imager photodiode with enhanced capacitance
    3.
    发明授权
    CMOS imager photodiode with enhanced capacitance 有权
    具有增强电容的CMOS成像光电二极管

    公开(公告)号：US08440490B2

    公开(公告)日：2013-05-14

    申请号：US13288686

    申请日：2011-11-03

    Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

    Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

    IPC: H01L31/18

    CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

    Abstract: A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface.

    Abstract translation: 一种制造像素传感器单元的方法，该像素传感器单元包括具有非横向放置的电荷收集区域的感光元件。 该方法包括在第一导电类型材料的衬底中形成沟槽凹槽，并用具有第二导电类型材料的材料填充沟槽凹槽。 然后将第二导电类型材料从填充的沟槽材料扩散到围绕沟槽的衬底区域，以形成非横向布置的电荷收集区域。 去除填充的沟槽材料以提供沟槽凹槽，并且用具有第一导电类型材料的材料填充沟槽凹槽。 表面注入层形成在具有第一导电类型材料的沟槽的任一侧。 沟槽型感光元件的收集区域由向外扩散的第二导电型材料形成，并与衬底表面隔离。

    Interface device with integrated solar cell(S) for power collection
    4.
    发明授权
    Interface device with integrated solar cell(S) for power collection 有权
    具有用于集电的集成太阳能电池（S）的接口装置

    公开(公告)号：US08384690B2

    公开(公告)日：2013-02-26

    申请号：US12779994

    申请日：2010-05-14

    Applicant: Brent A. Anderson ,  Mark D. Jaffe ,  Jed H. Rankin

    Inventor： Brent A. Anderson ,  Mark D. Jaffe ,  Jed H. Rankin

    IPC: G06F3/041 ,  G06F3/045 ,  H01L31/042

    CPC classification number: G06F3/042 ,  G06F3/041 ,  G06F3/0421 ,  G06F3/044 ,  G06F2203/04109

    Abstract: Disclosed herein are embodiments of an interface device (e.g., a display, touchpad, touchscreen display, etc.) with integrated power collection functions. In one embodiment, a solar cell or solar cell array can be located within a substrate at a first surface and an array of interface elements can also be located within the substrate at the first surface such that portions of the solar cell(s) laterally surround the individual interface elements or groups thereof. In another embodiment, a solar cell or solar cell array can be located within the substrate at a first surface and an array of interface elements can be located within the substrate at a second surface opposite the first surface (i.e., opposite the solar cell or solar cell array). In yet another embodiment, an array of diodes, which can function as either solar cells or sensing elements, can be within a substrate at a first surface and can be wired to allow for selective operation in either a power collection mode or sensing mode.

    Abstract translation: 这里公开了具有集成的功率收集功能的接口设备（例如，显示器，触摸板，触摸屏显示器等）的实施例。 在一个实施例中，太阳能电池或太阳能电池阵列可以位于第一表面的衬底内，并且界面元件阵列也可以位于第一表面的衬底内，使得太阳能电池的一部分横向包围 各个接口元件或其组合。 在另一个实施例中，太阳能电池或太阳能电池阵列可以位于第一表面的衬底内，并且界面元件的阵列可以位于衬底内的与第一表面相对的第二表面（即，与太阳能电池或太阳能 单元阵列）。 在另一个实施例中，可以用作太阳能电池或感测元件的二极管阵列可以在第一表面的衬底内，并且可以被布线以允许在电力收集模式或感测模式中的选择性操作。

    ISOLATION STRUCTURES FOR GLOBAL SHUTTER IMAGER PIXEL, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
    6.
    发明申请
    ISOLATION STRUCTURES FOR GLOBAL SHUTTER IMAGER PIXEL, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 有权
    全球快门像素像素分离结构，制造方法和设计结构

    公开(公告)号：US20120080732A1

    公开(公告)日：2012-04-05

    申请号：US12897230

    申请日：2010-10-04

    Applicant: Brent A. ANDERSON ,  Mark D. JAFFE

    Inventor： Brent A. ANDERSON ,  Mark D. JAFFE

    IPC: H01L31/112 ,  H01L31/18 ,  G06F17/50

    CPC classification number: H01L27/14603 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14689

    Abstract: Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region adjacent to the gate. The pixel sensor cell further includes an isolation region located below a channel region of the gate and about the photosensitive region, which prevents electrons collected in the photosensitive region to drift to the diffusion region.

    Abstract translation: 像素传感器单元，例如CMOS光学成像器，制造和设计结构的方法被提供有防止载流子漂移到扩散区域的隔离结构。 像素传感器单元包括感光区域和与感光区域相邻的栅极。 像素传感器单元还包括与栅极相邻的扩散区域。 像素传感器单元还包括位于栅极的沟道区域周围和感光区域下方的隔离区域，其防止在光敏区域中收集的电子漂移到扩散区域。

    Structure for pixel sensor cell that collects electrons and holes
    7.
    发明授权
    Structure for pixel sensor cell that collects electrons and holes 失效
    用于收集电子和空穴的像素传感器单元的结构

    公开(公告)号：US08039875B2

    公开(公告)日：2011-10-18

    申请号：US11850776

    申请日：2007-09-06

    Applicant: James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

    Inventor： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

    IPC: H01L27/148 ,  H01L31/062

    CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281 ,  H01L31/1037

    Abstract: The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

    Abstract translation: 本发明涉及一种像素传感器单元的设计结构。 像素传感器单元对于给定的光量大约使可用信号加倍。 具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上​​，以及p型收集阱区域 用于收集由撞击光子产生的孔的基板的表面。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。

    Random personalization of chips during fabrication
    8.
    发明授权
    Random personalization of chips during fabrication 有权
    制造期间芯片的随机个性化

    公开(公告)号：US08015514B2

    公开(公告)日：2011-09-06

    申请号：US12344725

    申请日：2008-12-29

    Applicant: Mark D. Jaffe ,  Stephen A. Mongeon ,  Leah M. P. Pastel ,  Jed H. Rankin

    Inventor： Mark D. Jaffe ,  Stephen A. Mongeon ,  Leah M. P. Pastel ,  Jed H. Rankin

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/66 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.

    Abstract translation: 公开了用于在制造期间随机个性化芯片的方法的实施例，个性化芯片结构和用于这种个性化芯片结构的设计结构。 实施例使用电子设备设计和制造过程来随机地或伪随机地在每个芯片上形成的特定电子设备的一个或多个实例中创建特定变化。 调整设备设计和制造过程，使得特定变化以某种预定概率发生，从而产生期望的硬件分布和个性化每个芯片。 所得到的个性化芯片可用于芯片的模态分配。 例如，当单芯片设计可用于支持多种应用时，芯片可以被个性化以允许排序。 所产生的个性化芯片也可以用于随机数生成，用于创建唯一的片上标识符，私钥等。

    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom
    9.
    发明授权
    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom 失效
    具有Cu布线的CMOS成像器和从其中消除高反射率界面的方法

    公开(公告)号：US07772028B2

    公开(公告)日：2010-08-10

    申请号：US11959841

    申请日：2007-12-19

    Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    IPC: H01L21/66

    CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

    Abstract: A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

    Abstract translation: CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

    Damascene copper wiring optical image sensor
    10.
    发明授权
    Damascene copper wiring optical image sensor 有权
    大马士革铜线接线光学图像传感器

    公开(公告)号：US07655495B2

    公开(公告)日：2010-02-02

    申请号：US11623977

    申请日：2007-01-17

    Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

    Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

    IPC: H01L21/00

    CPC classification number: H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

    Abstract: A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

    Abstract translation: CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，具有改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

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