Method and apparatus for calibrating DC-offsets in a direct conversion receiver
    1.
    发明授权
    Method and apparatus for calibrating DC-offsets in a direct conversion receiver 有权
    用于校准直接转换接收机中直流偏置的方法和装置

    公开(公告)号:US06868128B1

    公开(公告)日:2005-03-15

    申请号:US09610555

    申请日:2000-07-05

    申请人: Mark V. Lane

    发明人: Mark V. Lane

    摘要: A novel method and apparatus for calibrating DC offsets in a direct conversion receiver. The present DC offset calibration method and apparatus comprises a direct conversion receiver equipped with a frequency shifter means and a DC offset measurement and correction technique. In accordance with the present invention, DC offsets are calibrated in direct conversion receivers through an inventive method including two steps: a DC offset measurement step and a DC offset correction step. In the DC offset measurement step the frequency of a local oscillation signal (typically generated by a voltage-controlled oscillator (VCO)) is shifted by a selected frequency shift value during the inactive time intervals of the receiver. DC offsets are measured while the frequency of the down-conversion oscillation signal is shifted by the frequency shift value. Before the inactive time interval expires, the frequency of the down-conversion oscillator signal is shifted back to its original value. In the DC offset correction step of the present invention incoming signals are corrected using a correction means that removes the DC offset measured during the DC offset measurement step.

    摘要翻译: 一种用于校准直接转换接收机中的直流偏移的新颖方法和装置。 本直流偏移校准方法和装置包括配备有移频器装置和直流偏移测量和校正技术的直接转换接收器。 根据本发明,通过包括两个步骤的创造性方法在直接转换接收机中校准DC偏移:DC偏移测量步骤和DC偏移校正步骤。 在DC偏移测量步骤中,本地振荡信号(通常由压控振荡器(VCO)产生)的频率在接收机的非活动时间间隔期间偏移选定的频移值。 在降频转换振荡信号的频率偏移频移值的同时测量直流偏移。 在非活动时间间隔到期之前,下变频振荡器信号的频率被移回到其原始值。 在本发明的DC偏移校正步骤中,使用去除在DC偏移测量步骤期间测量的DC偏移的校正装置校正输入信号。

    Method and apparatus for automatic fast locking power conserving synthesizer
    2.
    发明授权
    Method and apparatus for automatic fast locking power conserving synthesizer 失效
    自动快速锁定节能合成器的方法和装置

    公开(公告)号:US07027796B1

    公开(公告)日:2006-04-11

    申请号:US09888108

    申请日:2001-06-22

    IPC分类号: H04B1/16

    摘要: A frequency synthesizer device with a fast off-to-lock time to enable intermittent operation and achieve power savings through automatic control of its On/Off sequence.A relatively fast off-to-lock time is achieved by controlling the sequence of how various components of the synthesizer are reactivated. The voltage controlled oscillator is reactivated, at first operating at its previous operating frequency prior to being deactivated. The phase frequency detector is inhibited while its input signals, a reference signal and a feedback signal, are activated. In a channel hopping communication scheme, the phase frequency detector coarsely tunes the synthesizer to its previous operating frequency, and then jumps to its new operating frequency. Another aspect of the invention provides improved channel locking by guaranteeing that the phase of the feedback signal in a phase lock loop initially lags the phase of the reference frequency signal at the phase frequency detector.

    摘要翻译: 频率合成器具有快速关断时间,可通过自动控制其On / Off序列实现间歇运行并实现功率节省。 通过控制合成器的各种组件如何重新启动的顺序来实现相对快速的非锁定时间。 压控振荡器被重新激活,首先在被禁用之前以其先前的工作频率工作。 当其输入信号,参考信号和反馈信号被激活时,相位频率检测器被禁止。 在频道跳频通信方案中,相位频率检测器将合成器粗调调谐到其先前的工作频率,然后跳到新的工作频率。 本发明的另一方面通过保证相位锁定回路中的反馈信号的相位最初滞后于相位频率检测器处的​​参考频率信号的相位来提供改进的通道锁定。