公开(公告)号：US08098510B2

公开(公告)日：2012-01-17

申请号：US12944790

申请日：2010-11-12

申请人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

发明人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1659

摘要： Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.

摘要翻译： 描述了可变电阻穿透访问方法。 所述方法包括通过使写入电流沿着第一方向通过磁性隧道结数据单元，将可变电阻数据单元从高电阻状态切换到低电阻状态。 写入电流由电耦合到可变电阻数据单元和源极线的晶体管提供。 写入电流在穿通模式下通过晶体管。

公开(公告)号：US20110156115A1

公开(公告)日：2011-06-30

申请号：US13042508

申请日：2011-03-08

申请人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

发明人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

IPC分类号： H01L29/02

CPC分类号： G11C11/1675 ,  G11C11/1659

摘要： Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.

摘要翻译： 描述了可变电阻穿透访问方法。 所述方法包括通过使写入电流沿着第一方向通过磁性隧道结数据单元，将可变电阻数据单元从高电阻状态切换到低电阻状态。 写入电流由电耦合到可变电阻数据单元和源极线的晶体管提供。 写入电流在穿通模式下通过晶体管。

公开(公告)号：US20100118589A1

公开(公告)日：2010-05-13

申请号：US12424065

申请日：2009-04-15

申请人： Andrew John Carter ,  Maroun Georges Khoury ,  Yong Lu ,  Roger Glenn Rolbiecki

发明人： Andrew John Carter ,  Maroun Georges Khoury ,  Yong Lu ,  Roger Glenn Rolbiecki

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C11/14

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675

摘要： A non-volatile memory cell array and associated method of use are disclosed. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.

摘要翻译： 公开了一种非易失性存储单元阵列和相关联的使用方法。 根据各种实施例，阵列包括耦合到共享交换设备的多个可编程电阻感测元件（RSE）。 开关器件具有公共源极区域和多个漏极区域，每个漏极区域与所述多个RSE连接到相关联的RSE。

公开(公告)号：US20120230084A1

公开(公告)日：2012-09-13

申请号：US13478174

申请日：2012-05-23

申请人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

发明人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1659

摘要： Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.

摘要翻译： 描述了可变电阻穿透访问方法。 所述方法包括通过使写入电流沿着第一方向通过磁性隧道结数据单元，将可变电阻数据单元从高电阻状态切换到低电阻状态。 写入电流由电耦合到可变电阻数据单元和源极线的晶体管提供。 写入电流在穿通模式下通过晶体管。

公开(公告)号：US20110170335A1

公开(公告)日：2011-07-14

申请号：US13071882

申请日：2011-03-25

申请人： Maroun Georges Khoury ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  YoungPil Kim

发明人： Maroun Georges Khoury ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  YoungPil Kim

IPC分类号： G11C11/34

CPC分类号： H01L27/101 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C2213/79 ,  H01L29/8618

摘要： A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.

摘要翻译： 提供一种用于访问非易失性存储单元的半导体器件。 在一些实施例中，半导体器件具有包括源极，漏极和阱的半导体层的垂直堆叠。 向半导体器件施加漏极 - 源极偏置电压在阱上产生穿透机构以引发源极和漏极之间的电流。

公开(公告)号：US07961497B2

公开(公告)日：2011-06-14

申请号：US12904288

申请日：2010-10-14

申请人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

发明人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1659

摘要： Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.

公开(公告)号：US07825478B2

公开(公告)日：2010-11-02

申请号：US12407823

申请日：2009-03-20

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： H01L29/00 ,  H01L21/425

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.

摘要翻译： 描述了用于电阻读出存储器的极性依赖开关。 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻式感测存储单元电连接到位触点。 源极接触和位触点用掺杂剂材料非对称地注入。

公开(公告)号：US20120175718A1

公开(公告)日：2012-07-12

申请号：US13422219

申请日：2012-03-16

申请人： Maroun Georges Khoury

发明人： Maroun Georges Khoury

IPC分类号： H01L29/82 ,  G11C11/00 ,  G11C7/00

CPC分类号： G11C13/003 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0073 ,  H01L27/226

摘要： A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate, a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, an emitter contact layer disposed in a second side of the semiconductor substrate, and a base layer separating the plurality of collector contacts from the emitter contact layer. Each collector contact is electrically isolated from each other. A resistive sense memory cells is electrically coupled to each collector contacts and a bit line. The base layer and the emitter contact layer provide an electrical path for the plurality of collector contacts.

摘要翻译： 电阻式感测存储装置包括具有半导体衬底的双极选择器件，设置在半导体衬底的第一侧中的多个集电极触点，设置在半导体衬底的第二侧的发射极接触层和基极层 从发射极接触层分离多个集电极触点。 每个集电极触点彼此电隔离。 电阻读出存储单元电耦合到每个集电极触点和位线。 基极层和发射极接触层为多个集电极触点提供电路。

公开(公告)号：US08208285B2

公开(公告)日：2012-06-26

申请号：US12502089

申请日：2009-07-13

申请人： Maroun Georges Khoury ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  YoungPil Kim

发明人： Maroun Georges Khoury ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  YoungPil Kim

IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C7/00 ,  G11C7/22 ,  G11C7/12 ,  G11C11/16

CPC分类号： H01L27/101 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C2213/79 ,  H01L29/8618

摘要： A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.

摘要翻译： 提供一种用于访问非易失性存储单元的半导体器件。 在一些实施例中，半导体器件具有包括源极，漏极和阱的半导体层的垂直堆叠。 向半导体器件施加漏极 - 源极偏置电压在阱上产生穿透机构以引发源极和漏极之间的电流。

公开(公告)号：US20120074466A1

公开(公告)日：2012-03-29

申请号：US12891982

申请日：2010-09-28

申请人： Dadi Setiadi ,  Peter Nicholas Manos ,  Hsing-Kuen Liou ,  Paramasivan Kamatchi Subramanian ,  Young Pil Kim ,  Hyung-Kyu Lee ,  Maroun Georges Khoury ,  Chulmin Jung

发明人： Dadi Setiadi ,  Peter Nicholas Manos ,  Hsing-Kuen Liou ,  Paramasivan Kamatchi Subramanian ,  Young Pil Kim ,  Hyung-Kyu Lee ,  Maroun Georges Khoury ,  Chulmin Jung

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L21/8239 ,  H01L21/823487 ,  H01L27/1052 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481

摘要： A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.

摘要翻译： 存储器阵列包括基本电路层和顺序堆叠以形成存储器阵列的多个存储器阵列层。 每个存储器阵列层电耦合到基极电路层。 每个存储器阵列层包括多个存储器单元。 每个存储单元包括电耦合到存储单元的垂直柱状晶体管。