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公开(公告)号：US20110025838A1
公开(公告)日：2011-02-03
申请号：US12839499
申请日：2010-07-20
申请人： Masaharu NINOMIYA
发明人： Masaharu NINOMIYA
CPC分类号： G01N21/9501 , G01N21/9505 , G06T7/0004 , G06T2207/10048 , G06T2207/10152 , G06T2207/20224 , G06T2207/30148
摘要： An object of the present invention is to simplify the defect inspection of an internal defect and front and rear surface defects in a wafer. A defect inspection method of the present invention includes: a first imaging step of taking a transmitted image of a wafer 1 by disposing two light source/image pickup units 4 and 5 equipped with a light source, an image pickup device and an optical system oppositely to each other across the wafer 1, irradiating infrared light from at least one of the light source/image pickup units 4 and 5 to the wafer 1, and receiving transmitted light from the wafer 1; a second imaging step of taking the respective reflected images of both wafer surfaces by irradiating infrared light or visible light from the light source/image pickup units 4 and 5 to the wafer 1 and receiving reflected light from the wafer 1; and an extraction step of extracting the defects in the wafer 1 on the basis of the transmitted image and the reflected images of both surfaces, thereby simultaneously detecting both an internal defect and front and rear surface defects in the wafer.
摘要翻译： 本发明的目的是简化晶片内部缺陷和前后表面缺陷的缺陷检查。 本发明的缺陷检查方法包括：第一成像步骤，通过将配备有光源，图像拾取装置和光学系统的两个光源/图像拾取单元4和5相对地设置来获取晶片1的透射图像 将来自光源/摄像单元4和5中的至少一个的红外光照射到晶片1并接收来自晶片1的透射光; 第二成像步骤，通过将来自光源/图像拾取单元4和5的红外光或可见光照射到晶片1并接收来自晶片1的反射光来获取两个晶片表面的各个反射图像; 以及基于透射图像和两个表面的反射图像提取晶片1中的缺陷的提取步骤，从而同时检测晶片中的内部缺陷和前后表面缺陷。
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公开(公告)号：US06261362B1
公开(公告)日：2001-07-17
申请号：US09395960
申请日：1999-09-14
IPC分类号： C30B1520
摘要： The objective of this invention is to provide a manufacturing method wherewith optimally low-COP substrates can be efficiently manufactured for epitaxial wafers in order to obtain high epitaxial surface quality that will not have an adverse effect on device characteristics. A phenomenon was discovered whereby COPs are eliminated by solution annealing or flattening when epitaxial films are formed on wafers wherein the density of grown-in defects (COPs) with a size of 0.130 &mgr;m or larger is 0.03 defects/cm2 or lower, the use of which phenomenon is characteristic of the invention. For example, by pulling a monocrystal while deliberately controlling the carbon concentration therein to within a prescribed high range, and employing wafers cut from silicon monocrystal ingots grown with a pulling speed wherewith no OSF-ring outer region is present in the wafer surface, wafers having the low COP densities noted above are obtained, and the COPs are eliminated by solution-annealing or flattening when forming the epitaxial film, wherefore high-quality epitaxial wafers can be manufactured with good yield.
摘要翻译： 本发明的目的是提供一种制造方法，其中为了获得不会对器件特性产生不利影响的高外延表面质量，可以有效地制造用于外延晶片的最佳低COP衬底。 发现一种现象，其中当在晶片上形成外延膜时，通过固溶退火或平坦化消除COP，其中尺寸为0.130μm或更大的生长缺陷（COP）的密度为0.03缺陷/ cm2或更低， 该现象是本发明的特征。 例如，通过在有意地将碳浓度控制在规定的高范围内的同时拉动单晶体，并且使用从在晶片表面没有OSF环外部区域的拉拔速度生长的硅单晶锭切割的晶片，具有 获得上述的低COP密度，并且在形成外延膜时通过固溶退火或平坦化来消除COP，因此可以以良好的成品率制造高品质的外延晶片。
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3.发明申请METHOD OF PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THE SAME 有权生产应变Si-SOI衬底和由其制造的应变Si-SOI衬底的方法公开(公告)号：US20090090933A1
公开(公告)日：2009-04-09
申请号：US11868296
申请日：2007-10-05
IPC分类号： H01L29/165 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/76243
摘要： A strained Si-SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.
摘要翻译： 提供了应变Si-SOI衬底及其制造方法，其中该方法包括以下步骤：在具有Si层13和掩埋氧化膜12的SOI衬底10上生长SiGe混晶层14; 在SiGe混晶层14的表面上形成保护膜15,16; 将光元素离子注入到Si层13和掩埋氧化物膜12之间的界面附近; 在400〜1000℃的温度下进行第一次热处理。 在氧化气氛下在不低于1050℃的温度下进行第二次热处理; 在不低于1050℃的温度下在惰性气氛下进行第三次热处理; 去除形成在表面上的Si氧化物膜18; 并形成应变Si层19。
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4.发明授权公开(公告)号：US07405142B2
公开(公告)日：2008-07-29
申请号：US10544310
申请日：2003-02-06
申请人： Ichiro Shiono , Masaharu Ninomiya , Hazumu Kougami
发明人： Ichiro Shiono , Masaharu Ninomiya , Hazumu Kougami
IPC分类号： H01L21/44
CPC分类号： H01L29/165 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L29/1054
摘要： A semiconductor substrate manufacturing method has a first layer formation process, a second layer formation process, a heat treatment process, and a polishing process; in the first layer formation process, the thickness of the first SiGe layer is set to less than twice the critical thickness, which is the film thickness at which dislocations appear and lattice relaxation occurs due to increasing film thickness; in the second layer formation process, the Ge composition ratio of the second SiGe layer is at least at the contact face with the first SiGe layer or with the Si layer, set lower than the maximum value of the Ge composition ratio in the first SiGe layer, and moreover, a gradient composition region in at least a portion of which the Ge composition ratio increases gradually toward the surface is formed. By this means, the penetrating dislocation density is kept low, surface roughness is low, and worsening of roughness at the surface and at interfaces due to heat treatment in device manufacturing processes or similar is prevented.
摘要翻译： 半导体衬底制造方法具有第一层形成工艺，第二层形成工艺，热处理工艺和抛光工艺; 在第一层形成工艺中，第一SiGe层的厚度被设定为小于临界厚度的两倍，临界厚度是由于增加膜厚而发生位错的膜厚度和晶格弛豫; 在第二层形成工艺中，第二SiGe层的Ge组成比至少在与第一SiGe层或Si层的接触面处设定为低于第一SiGe层中的Ge组成比的最大值 ，并且形成至少部分Ge组成比逐渐朝向表面增加的梯度组成区域。 通过这种方式，穿透位错密度保持较低，表面粗糙度低，并且防止了器件制造过程中类似的热处理在表面和界面处的粗糙度恶化。
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公开(公告)号：US20070166929A1
公开(公告)日：2007-07-19
申请号：US11649943
申请日：2007-01-05
IPC分类号： H01L21/336
CPC分类号： H01L21/7624 , H01L21/02532 , H01L21/0262
摘要： A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is formed on the SOI layer at a gradient of Ge concentration gradually decreasing toward the surface and then subjected to a heat treatment in an oxidizing atmosphere.
摘要翻译： 在包括绝缘层和SOI层的SOI晶片的绝缘层上形成晶格弛豫或部分晶格弛豫应变弛豫SiGe层的步骤中制造半导体晶片，其中至少上述 SiGe层以Ge浓度逐渐向表面逐渐减小的梯度形成在SOI层上，然后在氧化气氛中进行热处理。
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6.发明授权Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same 有权制造应变Si-SOI衬底及其制造的应变Si-SOI衬底的方法公开(公告)号：US07977221B2
公开(公告)日：2011-07-12
申请号：US11868296
申请日：2007-10-05
CPC分类号： H01L29/1054 , H01L21/76243
摘要： A strained Si—SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.
摘要翻译： 提供了应变Si-SOI衬底及其制造方法，其中该方法包括以下步骤：在具有Si层13和掩埋氧化膜12的SOI衬底10上生长SiGe混晶层14; 在SiGe混晶层14的表面上形成保护膜15,16; 将光元素离子注入到Si层13和掩埋氧化物膜12之间的界面附近; 在400〜1000℃的温度下进行第一次热处理。 在氧化气氛下在不低于1050℃的温度下进行第二次热处理; 在不低于1050℃的温度下在惰性气氛下进行第三次热处理; 去除形成在表面上的Si氧化物膜18; 并形成应变Si层19。
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7.发明申请Production method of strained silicon-SOI substrate and strained silicon-SOI substrate produced by same 审中-公开应变硅SOI衬底和应变硅SOI衬底的生产方法公开(公告)号：US20060214257A1
公开(公告)日：2006-09-28
申请号：US11388538
申请日：2006-03-23
CPC分类号： H01L21/26506 , H01L21/02381 , H01L21/02532 , H01L21/324 , H01L21/76251
摘要： A strained Si-SOI substrate is produced by a method comprising: growing a SiGe mixed crystal layer on an SOI substrate having a Si layer of not less than 5 nm in thickness and a buried oxide layer; forming a protective film on the SiGe mixed crystal layer; implanting light element ions into a vicinity of an interface between the silicon layer and the buried oxide layer; a first heat treatment for heat treating the substrate at a temperature of 400 to 1000° C. in an inert gas atmosphere; a second heat treatment for heat treating the substrate at a temperature not lower than 1050° C. in an oxidizing atmosphere containing chlorine; removing an oxide film from the surface of the substrate, and forming a strained silicon layer on the surface of the substrate.
摘要翻译： 通过以下方法制造应变Si-SOI衬底，该方法包括：在具有不小于5nm的Si层的SOI衬底上生长SiGe混合晶体层和掩埋氧化物层; 在SiGe混晶层上形成保护膜; 将光元素离子注入硅层和掩埋氧化物层之间的界面附近; 在惰性气体气氛中在400〜1000℃的温度下热处理基板的第一热处理; 在含有氯的氧化气氛中，在不低于1050℃的温度下对基材进行热处理的第二热处理; 从衬底的表面去除氧化膜，并在衬底的表面上形成应变硅层。
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8.发明授权Method of manufacturing semiconductor wafer by forming a strain relaxation SiGe layer on an insulating layer of SOI wafer 失效通过在SOI晶片的绝缘层上形成应变弛豫SiGe层来制造半导体晶片的方法公开(公告)号：US08110486B2
公开(公告)日：2012-02-07
申请号：US11649943
申请日：2007-01-05
IPC分类号： H01L21/20
CPC分类号： H01L21/7624 , H01L21/02532 , H01L21/0262
摘要： A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is formed on the SOI layer at a gradient of Ge concentration gradually decreasing toward the surface and then subjected to a heat treatment in an oxidizing atmosphere.
摘要翻译： 在包括绝缘层和SOI层的SOI晶片的绝缘层上形成晶格弛豫或部分晶格弛豫应变弛豫SiGe层的步骤中制造半导体晶片，其中至少上述 SiGe层以Ge浓度逐渐向表面逐渐减小的梯度形成在SOI层上，然后在氧化气氛中进行热处理。
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公开(公告)号：US20090047526A1
公开(公告)日：2009-02-19
申请号：US11840615
申请日：2007-08-17
CPC分类号： H01L21/76254
摘要： A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided. The method includes the steps of: (a) forming an SiGe mixed crystal layer 12 and a first Si layer 13 in this order on the surface of a silicon wafer 11; (b) forming an SiO2 layer 16 on top of the first Si layer and/or a support wafer 14; (c) forming a layered product 17 by stacking the silicon wafer and the support wafer with the SiO2 layer being placed therebetween; (d) forming a second Si layer 18 by thinning the silicon wafer of the layered product; (e) implanting hydrogen ion and/or rare gas ion, such that ionic concentration peaks in a predetermined area; (f) subjecting the layered product to a first heat treatment; and (g) carrying out a second heat treatment following the first heat treatment, thereby relaxing the SiGe mixed crystal layer and diffusing Ge through portions of the first Si layer and the second Si layer.
摘要翻译： 本发明提供一种制造半导体晶片的方法，该半导体晶片具有具有足够的拉伸应变和很少的晶体缺陷的应变Si层，同时实现相对简单的分层结构。 该方法包括以下步骤：（a）在硅晶片11的表面上依次形成SiGe混晶层12和第一Si层13; （b）在第一Si层和/或支撑晶片14的顶部上形成SiO2层16; （c）通过将硅晶片和支撑晶片叠置在其间的SiO 2层来形成层叠体17; （d）通过使层叠体的硅晶片变薄来形成第二Si层18; （e）植入氢离子和/或稀有气体离子，使得离子浓度在预定区域中峰值; （f）对层叠体进行第一次热处理; 和（g）在第一热处理之后进行第二热处理，从而使SiGe混晶层松弛，并通过第一Si层和第二Si层的一部分扩散Ge。
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10.发明授权Method for manufacturing semiconductor wafer including a strained silicon layer 有权包括应变硅层的半导体晶片的制造方法公开(公告)号：US07767548B2
公开(公告)日：2010-08-03
申请号：US11840615
申请日：2007-08-17
IPC分类号： H01L21/30
CPC分类号： H01L21/76254
摘要： A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided. The method includes the steps of: (a) forming an SiGe mixed crystal layer 12 and a first Si layer 13 in this order on the surface of a silicon wafer 11; (b) forming an SiO2 layer 16 on top of the first Si layer and/or a support wafer 14; (c) forming a layered product 17 by stacking the silicon wafer and the support wafer with the SiO2 layer being placed therebetween; (d) forming a second Si layer 18 by thinning the silicon wafer of the layered product; (e) implanting hydrogen ion and/or rare gas ion, such that ionic concentration peaks in a predetermined area; (f) subjecting the layered product to a first heat treatment; and (g) carrying out a second heat treatment following the first heat treatment, thereby relaxing the SiGe mixed crystal layer and diffusing Ge through portions of the first Si layer and the second Si layer.
摘要翻译： 本发明提供一种制造半导体晶片的方法，该半导体晶片具有具有足够的拉伸应变和很少的晶体缺陷的应变Si层，同时实现相对简单的分层结构。 该方法包括以下步骤：（a）在硅晶片11的表面上依次形成SiGe混晶层12和第一Si层13; （b）在第一Si层和/或支撑晶片14的顶部上形成SiO2层16; （c）通过将硅晶片和支撑晶片叠置在其间的SiO 2层来形成层叠体17; （d）通过使层叠体的硅晶片变薄来形成第二Si层18; （e）植入氢离子和/或稀有气体离子，使得离子浓度在预定区域中峰值; （f）对层叠体进行第一次热处理; 和（g）在第一热处理之后进行第二热处理，从而使SiGe混晶层松弛，并通过第一Si层和第二Si层的一部分扩散Ge。
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