Molding attaching structure, molding attaching clip, and molding
    5.
    发明申请
    Molding attaching structure, molding attaching clip, and molding 有权
    成型安装结构,成型安装夹和成型

    公开(公告)号:US20070182214A1

    公开(公告)日:2007-08-09

    申请号:US10590051

    申请日:2005-02-22

    IPC分类号: B62D25/06

    摘要: A molding attaching clip 30 includes a fixed portion 31 to be fixed in a groove 15 of a roof panel 10, a pair of elastically deformable wall portions 32 which are erected from the fixed portion 31, a pair of engaging portions 33 which are provided on the pair of wall portions 32, and an elastically deformable guide portion 36 which is projected from the fixed portion 31. A roof molding 20 includes a head portion 21 for covering the groove 15, and a projected portion 27 which is protruded from a back face of the head portion 21. The projected portion has a pair of locking portions 24 which are provided on both side faces thereof, and a receiving groove 26 which is formed in the projected portion 27. On occasion of engaging the roof molding 20 with the molding attaching clip 30, the roof molding 20 is positioned so that the pair of locking portions 24 can be engaged with the pair of engaging portions 33, by butting the receiving groove 26 against the guide portion 36.

    摘要翻译: 成型安装夹30包括固定在顶板10的槽15中的固定部分31,从固定部分31竖立的一对可弹性变形的壁部分32,一对接合部分33, 一对壁部32以及从固定部31突出的可弹性变形的引导部36。 屋顶模制件20包括用于覆盖槽15的头部21和从头部21的背面突出的突出部27。 突出部分具有设置在其两个侧面上的一对锁定部分24和形成在突出部分27中的接收槽26。 在将屋顶模制件20与模制安装夹30接合的情况下,屋顶模制件20被定位成使得一对锁定部分24能够与一对接合部分33接合,通过将接收槽26抵靠引导部分 36。

    Orthogonal frequency division multiplexing receiver device
    7.
    发明授权
    Orthogonal frequency division multiplexing receiver device 有权
    正交频分复用接收机设备

    公开(公告)号:US06954421B2

    公开(公告)日:2005-10-11

    申请号:US09785939

    申请日:2001-02-15

    摘要: After the OFDM signal for MMAC is received by a receiving unit , an FFT processing unit converts such OFDM signal into the signal Y(l, k) in the frequency axis direction. A data extracting unit extracts a data signal Y(l, kd) and a pilot extracting unit extracts a pilot signal Y(l, kp). A complex dividing unit divides the extracted pilot signal with a pilot signal X(l, kp) having the identical amplitude and phase as that in the transmitting side. An interpolating unit performs a linear interpolation by using a transmission path response H(l, kp) of the pilot signal in order to calculate the transmission path estimation value H′(l, k) of the data signal. A complex dividing unit divides the extracted data signal with the transmission path estimation value of the data signal in order to calculate the data signal Y′(l, kd) that is compensated in the amplitude and phase.

    摘要翻译: 在由接收单元接收到用于MMAC的OFDM信号之后,FFT处理单元将这样的OFDM信号转换为频率轴方向上的信号Y(1,k)。 数据提取单元提取数据信号Y(1,kd),导频提取单元提取导频信号Y(l,kp)。 复分割单元用与发送侧具有相同幅度和相位的导频信号X(1,kp)对提取的导频信号进行分频。 内插单元通过使用导频信号的传输路径响应H(1,kp)来执行线性插值,以便计算数据信号的传输路径估计值H'(1,k)。 复分割单元用提取的数据信号与数据信号的传输路径估计值进行分割,以计算在幅度和相位上被补偿的数据信号Y'(1,kd)。

    Signal synchronization method and receiver device for packet communication
    8.
    发明授权
    Signal synchronization method and receiver device for packet communication 有权
    用于分组通信的信号同步方法和接收机设备

    公开(公告)号:US07158541B2

    公开(公告)日:2007-01-02

    申请号:US09792517

    申请日:2001-02-23

    IPC分类号: H04J3/06 H04L7/00

    摘要: A receiver device for a packet communication system receives a packet signal appended at its head with a known number (N) of repetition signals. A correlation value of a received signal is outputted from a normalizing correlator and compared with a threshold value in a comparator. The output of the comparator is inputted to a synchronization signal generating circuit, which includes M (≦N−1) delay elements connected in series and an AND circuit for taking the logical product of the outputs of the delay elements. When the output of the comparator is high-level and the outputs of the M delay elements 431 are also all high-level, a synchronization signal at symbol timing is outputted from the AND circuit.

    摘要翻译: 用于分组通信系统的接收机设备以已知数量(N)个重复信号接收在其头部附加的分组信号。 从归一化相关器输出接收信号的相关值,并与比较器中的阈值进行比较。 比较器的输出被输入到同步信号发生电路,该同步信号产生电路包括串联连接的M(<= N-1)个延迟元件和用于取得延迟元件的输出的逻辑积的“与”电路。 当比较器的输出为高电平,并且M个延迟元件431的输出也全部为高电平时,从“与”电路输出符号定时的同步信号。