公开(公告)号：US07807534B2

公开(公告)日：2010-10-05

申请号：US12033468

申请日：2008-02-19

申请人： Hideaki Tanaka ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Shigeharu Yamagami

发明人： Hideaki Tanaka ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Shigeharu Yamagami

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/7828

摘要： A method for producing a semiconductor device includes forming a first hetero-semiconductor layer as a hetero-junction to a surface of a silicon carbide epitaxial layer. This layer is composed of polycrystalline silicon having a band gap different from that of the silicon carbide epitaxial layer. An etching stopper layer composed of a material having a different etching rate from that of the polycrystalline silicon is formed on the surface of the first hetero-semiconductor layer. A second hetero-semiconductor layer composed of polycrystalline silicon is formed so that the second hetero-semiconductor layer contacts the surface of the first hetero-semiconductor layer and the etching stopper layer. The etching stopper layer is removed, the first hetero-semiconductor layer is thermally oxidized, and the thermally oxidized portion is then removed.

摘要翻译： 一种制造半导体器件的方法包括：将第一异质半导体层形成为与碳化硅外延层的表面的异质结。 该层由具有与碳化硅外延层的带隙不同的带隙的多晶硅构成。 在第一异质半导体层的表面上形成由具有与多晶硅的蚀刻速率不同的蚀刻速率的材料构成的蚀刻停止层。 形成由多晶硅构成的第二异质半导体层，使得第二异质半导体层与第一异质半导体层和蚀刻停止层的表面接触。 除去蚀刻停止层，将第一异质半导体层热氧化，然后除去热氧化部分。

公开(公告)号：US07781786B2

公开(公告)日：2010-08-24

申请号：US11783577

申请日：2007-04-10

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L29/22 ,  H01L33/00 ,  H01L29/732 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/739 ,  H01L29/861 ,  H01L31/107 ,  H01L29/864

CPC分类号： H01L29/7808 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/6606 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/8618 ,  H01L29/872

摘要： Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.

摘要翻译： 设定第二半导体区域的杂质浓度，使得当将预定的反向偏压施加到由第一半导体区域和第二半导体区域构成的异质结二极管时，至少在异种结区以外的击穿电压 异质结二极管是半导体器件的击穿电压。

公开(公告)号：US20090233408A1

公开(公告)日：2009-09-17

申请号：US11988944

申请日：2006-06-26

申请人： Shigeharu Yamagami ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Yoshio Shimoida

发明人： Shigeharu Yamagami ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Yoshio Shimoida

IPC分类号： H01L21/336 ,  H01L21/22

CPC分类号： H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/7827

摘要： A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.

摘要翻译： 一种制造具有多晶硅层（5）的半导体器件的方法包括： 在多晶硅层（5）上形成掩模层（7）的步骤; 形成设置在掩模层（7）的侧面并覆盖多晶硅层（6）的一部分的侧壁（8）的步骤; 通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模将杂质（52）掺杂到多晶硅层（5）中的步骤; 以及通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模来蚀刻多晶硅层（5,6）的步骤。

公开(公告)号：US20090140264A1

公开(公告)日：2009-06-04

申请号：US12325377

申请日：2008-12-01

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L29/24 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0623 ,  H01L29/0642 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/7828

摘要： A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved at the time of interruption, and at the same time, the generation of the hot spot where in a specific portion is prevented at the time of conduction to suppress deterioration in a specific portion, thereby ensuring a long-term reliability. Further, when the semiconductor chip is used in an L load circuit or the like, for example, at the time of conduction or during a transient response time to the interrupted state, in an index such as a short resistant load amount and an avalanche resistant amount, which are indexes of a breakdown tolerance when overcurrent or overvoltage occurs, the current concentration on a specific portion can be prevented, and thus, these breakdown tolerances can also be improved.

摘要翻译： 作为将反向偏置电流保持集中在凸角上的电流 - 浓度释放区域的异质半导体角区域设置在异质半导体区域中。 由此，可以防止凸角上的电流集中。 结果，在中断时可以提高中断性能，同时，在导通时防止特定部位的热点的产生，抑制特定部分的劣化，从而确保 长期可靠。 此外，例如在导通时或半导体芯片用于L负载电路等时，例如，在短时间响应时间到中断状态时，以诸如短路负载量和雪崩阻抗的指标 量是当发生过电流或过电压时的击穿容限的指标，可以防止特定部分上的电流浓度，因此也可以提高这些击穿公差。

公开(公告)号：US07476590B2

公开(公告)日：2009-01-13

申请号：US11231799

申请日：2005-09-22

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

IPC分类号： H01L21/336

CPC分类号： H01L29/7828 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/7827

摘要： A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer remains to be not etched with a predetermined thickness; oxidizing an exposed parts of the hetero semiconductor layer; forming the hetero semiconductor region by etching a oxidized film formed in the oxidizing; and forming the gate insulating film in a way that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body. The bandgap of the hetero semiconductor layer is different from that of the semiconductor substrate body. The gate electrode is arranged in a junction part between the hetero semiconductor region and the semiconductor substrate body with the gate insulating film interposed between the gate electrode and the junction part.

摘要翻译： 一种制造半导体器件的方法，其特征在于：在至少在第一导电类型的半导体衬底主体的主表面上形成杂半导体层; 通过使用具有开口的掩模层选择性地蚀刻异质半导体层，使得异质半导体层保持不被预定厚度蚀刻; 氧化杂半导体层的暴露部分; 通过蚀刻氧化膜形成的氧化膜来形成异质半导体区域; 以及栅极绝缘膜与异质半导体区域和半导体衬底本体紧密接触的方式形成栅极绝缘膜。 异质半导体层的带隙与半导体衬底本体的带隙不同。 栅电极配置在异质半导体区域和半导体衬底本体之间的接合部分中，栅极绝缘膜介于栅电极和接合部分之间。

公开(公告)号：US20080210938A1

公开(公告)日：2008-09-04

申请号：US11961221

申请日：2007-12-20

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L29/778 ,  H01L29/24

CPC分类号： H01L27/088 ,  H01L21/32139 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7828

摘要： A semiconductor device with superior long-term reliability is disclosed that alleviates current concentration into a switch structure arranged at an outermost portion. The semiconductor device comprises hetero semiconductor regions formed of polycrystalline silicon having a band gap width different from that of a drift region and hetero-adjoined with the drift region, a gate insulation film, a gate electrode adjoined to the gate insulation film, a source electrode connected to a source contact portion of the hetero semiconductor regions and an outermost switch structure and a repeating portion switch structure with a drain electrode connected to a substrate region. In a conduction state, the outermost switch structure comprises a mechanism in which the current flowing at the outermost switch structure becomes smaller than the current flowing at the repeating portion switch structure.

摘要翻译： 公开了一种具有优异的长期可靠性的半导体器件，其将电流浓度减轻到布置在最外部的开关结构。 半导体器件包括由多晶硅形成的异质半导体区域，该多晶硅的带隙宽度与漂移区域的带隙宽度不同，并且与漂移区域异质相邻，栅极绝缘膜，与栅极绝缘膜邻接的栅电极，源电极 连接到异质半导体区域的源极接触部分和最外面的开关结构以及具有连接到衬底区域的漏电极的重复部分开关结构。 在导通状态下，最外面的开关结构包括一种机构，其中在最外侧开关结构处流动的电流变得小于在重复部分开关结构处流动的电流。

公开(公告)号：US20080108211A1

公开(公告)日：2008-05-08

申请号：US11907401

申请日：2007-10-11

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L21/283

CPC分类号： H01L29/267 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7828

摘要： A method for producing a semiconductor device which includes: a semiconductor base, a hetero semiconductor region made of a semiconductor material different in band gap from a semiconductor material for the semiconductor base, and so configured as to form a hetero junction in combination with the semiconductor base, a gate insulating film so configured as to contact with the hetero junction between the semiconductor base and the hetero semiconductor region, a gate electrode so configured as to contact with the gate insulating film, a source electrode connected to the hetero semiconductor region, and a drain electrode connected to the semiconductor base. The method includes: forming the following in a self-aligning manner, by using a certain mask material: a source contact hole for the source electrode, and the gate electrode.

摘要翻译： 一种半导体器件的制造方法，其特征在于，包括：半导体基底，与半导体基板的半导体材料的带隙不同的半导体材料构成的异质半导体区域，并且与半导体基板结合形成异质结 基底，被配置为与半导体基底和异质半导体区域之间的异质结接触的栅极绝缘膜，被配置为与栅极绝缘膜接触的栅极电极，连接到异质半导体区域的源极电极，以及 连接到半导体基底的漏电极。 该方法包括：通过使用某种掩模材料：源电极的源极接触孔和栅电极，以自对准的方式形成以下。

公开(公告)号：US20080023707A1

公开(公告)日：2008-01-31

申请号：US11493604

申请日：2006-07-27

申请人： Hideaki Tanaka ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Tetsuya Hayashi ,  Shigeharu Yamagami

发明人： Hideaki Tanaka ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Tetsuya Hayashi ,  Shigeharu Yamagami

IPC分类号： H01L31/0312 ,  H01L21/00

CPC分类号： H01L29/66068 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/6606 ,  H01L29/7827 ,  H01L29/861

摘要： A semiconductor device, includes: 1) an electric field relaxing area, including: i) a hetero junction formed by the followings: a) a first semiconductor material, and b) a second semiconductor material different from the first semiconductor material in band gap, and ii) an impurity introducing area so formed on the first semiconductor material as to contact the hetero junction.

摘要翻译： 一种半导体器件，包括：1）电场缓和区域，包括：i）通过以下方式形成的异质结：a）第一半导体材料，以及b）与带隙中的第一半导体材料不同的第二半导体材料， 以及ii）如此形成在第一半导体材料上以与异质结接触的杂质引入区域。

公开(公告)号：US20070252174A1

公开(公告)日：2007-11-01

申请号：US11790380

申请日：2007-04-25

申请人： Shigeharu Yamagami ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Tetsuya Hayashi ,  Hideaki Tanaka

发明人： Shigeharu Yamagami ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Tetsuya Hayashi ,  Hideaki Tanaka

IPC分类号： H01L31/00

CPC分类号： H01L29/66068 ,  H01L21/046 ,  H01L29/42376 ,  H01L29/7827

摘要： After a polycrystalline silicon as a hetero-semiconductor region forming a heterojunction with a semiconductor base is formed on an epitaxial layer configuring the semiconductor base, the unevenness on the surface of the polycrystalline silicon is planarized before a gate insulating film is formed. Alternatively, as the hetero-semiconductor region, amorphous or microcrystal hetero-semiconductor of which crystal grain diameter is small is used. When an amorphous or microcrystal hetero-semiconductor is deposited as the hetero-semiconductor region, a recrystallization annealing process of transforming into the polycrystalline silicon can be applied after the deposition. As a material of the semiconductor base, silicon carbide, gallium nitride or diamond can be used. As a material of the hetero-semiconductor region, silicon, silicon germanium, germanium, or gallium arsenide can be used.

摘要翻译： 在构成半导体基底的外延层上形成多晶硅作为形成与半导体基底的异质结的异质半导体区域之后，在形成栅极绝缘膜之前，将多晶硅的表面上的不平坦度平坦化。 或者，作为异质半导体区域，使用结晶粒径小的非晶或微晶异质半导体。 当非晶或微晶异质半导体作为异质半导体区域沉积时，可以在沉积之后施加转化为多晶硅的再结晶退火工艺。 作为半导体基底的材料，可以使用碳化硅，氮化镓或金刚石。 作为异质半导体区域的材料，可以使用硅，硅锗，锗或砷化镓。

公开(公告)号：US20060118818A1

公开(公告)日：2006-06-08

申请号：US11289460

申请日：2005-11-30

申请人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Tetsuya Hayashi ,  Toshiro Shinohara ,  Shigeharu Yamagami

发明人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Tetsuya Hayashi ,  Toshiro Shinohara ,  Shigeharu Yamagami

IPC分类号： H01L29/732

CPC分类号： H01L29/7398 ,  H01L29/0834 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/7395 ,  H01L29/7397

摘要： An aspect of the present invention provides a semiconductor device that includes, a first semiconductor body of a first conductivity type, a first switching mechanism provided on the first semiconductor body, configured and arranged to switch on/off current flowing through the semiconductor device, and a first reverse-blocking heterojunction diode provided on the semiconductor body, configured and arranged to block current reverse to the current switched on/off by the first switching mechanism.

摘要翻译： 本发明的一个方面提供一种半导体器件，其包括：第一导电类型的第一半导体本体，设置在第一半导体本体上的第一开关机构，被配置和布置成用于接通流过半导体器件的导通/截止电流;以及 设置在所述半导体本体上的第一反向阻挡异质结二极管，被配置和布置成阻止与所述第一开关机构相反的电流接通/断开。