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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07599232B2

    公开(公告)日：2009-10-06

    申请号：US11826109

    申请日：2007-07-12

    申请人： Masaki Miyata

    发明人： Masaki Miyata

    IPC分类号： G11C7/00

    CPC分类号： G11C8/08 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C11/413 ,  G11C2211/4067 ,  G11C2211/4068

    摘要： A word line driving circuit includes first, second, and third MOS transistors. Gates of the first and second transistors are commonly connected. Sources of the first and second transistors are connected to different power supplies. The third transistor is connected between the drains of the first and second transistors. A connection node between the drains of the second and third transistors is connected to a word line. When the input signal is set to a high level and the second transistor is turned on, a potential lower than a high level of the input signal is supplied to a gate of the third MOS transistor. A signal with a high level thereof being lower than a high level of the input signal, or a fixed GND potential is supplied to the gate of the third transistor.

    摘要翻译： 字线驱动电路包括第一，第二和第三MOS晶体管。 第一和第二晶体管的栅极通常连接。 第一和第二晶体管的源极连接到不同的电源。 第三晶体管连接在第一和第二晶体管的漏极之间。 第二和第三晶体管的漏极之间的连接节点连接到字线。 当输入信号被设置为高电平并且第二晶体管导通时，低于输入信号的高电平的电位被提供给第三MOS晶体管的栅极。 其高电平的信号低于输入信号的高电平，或者将固定的GND电位提供给第三晶体管的栅极。

    Semiconductor memory device
    2.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20080049539A1

    公开(公告)日：2008-02-28

    申请号：US11826109

    申请日：2007-07-12

    申请人： Masaki Miyata

    发明人： Masaki Miyata

    IPC分类号： G11C8/00 ,  H03K3/00

    CPC分类号： G11C8/08 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C11/413 ,  G11C2211/4067 ,  G11C2211/4068

    摘要： Disclosed is a word line driving circuit which includes a first MOS transistor and a second MOS transistor having mutually different conductivity types and a third MOS transistor of a conductivity type which is the same as that of the first MOS transistor. Gates of the first and second MOS transistors are connected in common for receiving an input signal. Sources of the first and second MOS transistors are connected to a first power supply and a second power supply, respectively. The third MOS transistor is connected between a drain of the first MOS transistor and a drain of the second MOS transistor. A connection node between the drain of the second MOS transistor and a drain of the third MOS transistor is connected to a word line. When the input signal is set to a high level and when the second transistor is turned on, a potential lower than a high level of the input signal is supplied to a gate of the third MOS transistor. A signal with a high level thereof being lower than a high level of the input signal, or a fixed GND potential is supplied to the gate of the third MOS transistor.

    摘要翻译： 公开了一种字线驱动电路，其包括具有不同导电类型的第一MOS晶体管和第二MOS晶体管和与第一MOS晶体管相同的导电类型的第三MOS晶体管。 第一和第二MOS晶体管的栅极共同连接用于接收输入信号。 第一和第二MOS晶体管的源极分别连接到第一电源和第二电源。 第三MOS晶体管连接在第一MOS晶体管的漏极和第二MOS晶体管的漏极之间。 第二MOS晶体管的漏极和第三MOS晶体管的漏极之间的连接节点连接到字线。 当输入信号被设置为高电平并且当第二晶体管导通时，低于输入信号的高电平的电位被提供给第三MOS晶体管的栅极。 其高电平的信号低于输入信号的高电平，或者将固定的GND电位提供给第三MOS晶体管的栅极。