公开(公告)号：US20110184401A1

公开(公告)日：2011-07-28

申请号：US13054439

申请日：2009-07-10

申请人： Kansei Iwata ,  Yasushi Iwata ,  Taisuke Nagasawa ,  Masafumi Kawamura ,  Yotaro Izumi ,  Masanori Inoue ,  Norimasa Tsukada ,  Hideki Yashiro

发明人： Kansei Iwata ,  Yasushi Iwata ,  Taisuke Nagasawa ,  Masafumi Kawamura ,  Yotaro Izumi ,  Masanori Inoue ,  Norimasa Tsukada ,  Hideki Yashiro

IPC分类号： A61B18/02

CPC分类号： A61B18/02 ,  A61B34/10 ,  A61B2018/00041 ,  A61B2018/0275 ,  A61B2018/0281

摘要： The present invention relates to a treatment device utilized in the freezing treatment method and its treatment planning device, and has an object to settle a freezing period·defrosting period according to a size of a treatment portion.A cryotherapy device comprises a gas supply-exhaust system 100, a control system 200 therefore and a freezing probe system 300. The gas supply-exhaust system 100 supplies a freezing gas and a defrosting gas to a probe 60 of the freezing probe system 300 to freeze and defrost the treatment portion surrounding the tip of the probe 60 by the Joule·Thomson effect. The control system 200 controls the gas supply-exhaust system 100 and makes treatment planning data for this control. The treatment planning data includes a freezing·defrosting sequence to determine the freezing period and the defrosting period. The determination of this sequence is performed by the computer in the control system 200. Further, this sequence is determined corresponding to the focus treatment size according to the freezing·defrosting characteristics of the tissue.

摘要翻译： 本发明涉及一种在冷冻处理方法及其处理计划装置中使用的处理装置，其目的是根据处理部的尺寸来设定冷冻期·除霜期间。 冷冻治疗装置包括气体供给 - 排气系统100，因此控制系统200和冷冻探针系统300.气体供应 - 排气系统100将冷冻气体和除霜气体供应到冷冻探针系统300的探针60，以 通过焦耳·汤姆森效应冻结和除霜探针60的尖端周围的处理部分。 控制系统200控制供气排气系统100，并且进行该控制的处理计划数据。 治疗计划数据包括冷冻·除霜顺序，以确定冷冻期和除霜期。 该序列的确定由控制系统200中的计算机执行。此外，根据组织的冻结·除霜特性，对应于焦点处理尺寸确定该顺序。

公开(公告)号：US07911020B2

公开(公告)日：2011-03-22

申请号：US12171193

申请日：2008-07-10

申请人： Yasushi Niimura ,  Takashi Kobayashi ,  Masanori Inoue ,  Yasuhiko Onishi

发明人： Yasushi Niimura ,  Takashi Kobayashi ,  Masanori Inoue ,  Yasuhiko Onishi

IPC分类号： H01L29/02

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41741 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has an active portion having at least one well region in a semiconductor layer, and a breakdown voltage maintaining structure surrounding the active portion. The maintaining structure includes a conductor layer over each of a plurality of guard rings with an insulating film interposed in between and connected to the respective guard ring. An inner side end portion of each conductor layer projects over the immediate adjacent inner side guard ring. The impurity concentration of the guard rings is set between the impurity concentrations of the semiconductor layer and the well regions. A field plate can extend over the innermost conductor layer with the insulating film interposed in between. The field plate is in contact with the outermost well region and is in contact with the first conductor layer. The outer side end of the field plate extends outwardly beyond an outer side end of the innermost conductor layer. With these arrangements, the guard rings can be shortened and the chip size can be reduced. Furthermore, the device can be made less susceptible to external charge.

摘要翻译： 半导体器件具有在半导体层中具有至少一个阱区的有源部分和围绕有源部分的击穿电压保持结构。 保持结构包括在多个保护环中的每一个上的导体层，绝缘膜介于其间并连接到相应的保护环。 每个导体层的内侧端部突出在紧邻的内侧保护环上。 保护环的杂质浓度设定在半导体层和阱区的杂质浓度之间。 场板可以在绝缘膜介于其间的最内侧的导体层上延伸。 场板与最外层区域接触并与第一导体层接触。 场板的外侧端部向外延伸超出最内侧导体层的外侧端部。 通过这些布置，可以缩短保护环，并且可以减小芯片尺寸。 此外，可以使该装置不易受到外部充电的影响。

公开(公告)号：US07372111B2

公开(公告)日：2008-05-13

申请号：US11197751

申请日：2005-08-04

申请人： Yasuhiko Onishi ,  Takeyoshi Nishimura ,  Yasushi Niimura ,  Masanori Inoue

发明人： Yasuhiko Onishi ,  Takeyoshi Nishimura ,  Yasushi Niimura ,  Masanori Inoue

IPC分类号： H01L29/72

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/7802

摘要： The superjunction semiconductor device includes a drain drift section, which includes a first alternating conductivity type layer formed of first n-type regions and first p-type regions arranged alternately. The device also includes a peripheral section around the drain drift section, which includes a second alternating conductivity type layer formed of second n-type regions and second p-type regions arranged alternately. The peripheral section further includes a third alternating conductivity type layer in its surface portion. The third alternating conductivity type layer is formed of third n-type regions and third p-type regions arranged alternately. At least the peripheral section is configured to improve the avalanche withstanding capability over the entire device.

摘要翻译： 超级结半导体器件包括漏极漂移部分，其包括由第一n型区域和交替布置的第一p型区域形成的第一交变导电类型层。 该装置还包括围绕漏极漂移部分的周边部分，其包括由交替布置的第二n型区域和第二p型区域形成的第二交变导电类型层。 外围部分还包括在其表面部分中的第三交变导电类型层。 第三交变导电型层由交替布置的第三n型区域和第三p型区域形成。 至少外围部分被配置为提高整个设备上的雪崩承受能力。

公开(公告)号：US20080079119A1

公开(公告)日：2008-04-03

申请号：US11678384

申请日：2007-02-23

申请人： Masanori INOUE

发明人： Masanori INOUE

IPC分类号： H01L29/30 ,  H01L21/263

CPC分类号： H01L21/263 ,  H01L29/32 ,  H01L29/66136 ,  H01L29/861

摘要： A p-n junction is formed at the interface of a low-concentration n-type impurity layer 3 and a p-type diffusion region 5 in the vicinity of the upper major surface of an n-type semiconductor substrate 2 of a semiconductor device 1. A mask 15 composed of an absorber is placed on the upper major surface of the semiconductor device 1, and electron beams are radiated. Thereafter, heat treatment is conducted. As a result, the peak of the crystal lattice defect densities is present in the vicinity of the upper major surface of the n-type semiconductor substrate 2, and the crystal lattice defect densities are decreasingly distributed toward the lower major surface. Thereby, a semiconductor device that can minimize the variation of the breakdown voltage characteristics of the p-n junction of the diode, and can control the optimum carrier lifetime can be obtained.

摘要翻译： 在半导体器件1的n型半导体衬底2的上表面附近的低浓度n型杂质层3和p型扩散区域5的界面处形成p-n结。 由半导体器件1的上表面放置由吸收体构成的掩模15，照射电子束。 之后，进行热处理。 结果，晶格缺陷密度的峰值存在于n型半导体衬底2的上表面附近，并且晶格缺陷密度向下主表面逐渐分布。 由此，可以获得能够最小化二极管的p-n结的击穿电压特性的变化并能够控制最佳载流子寿命的半导体器件。

公开(公告)号：US06943410B2

公开(公告)日：2005-09-13

申请号：US10170216

申请日：2002-06-12

申请人： Tatsuhiko Fujihira ,  Takashi Kobayashi ,  Hitoshi Abe ,  Yasushi Niimura ,  Masanori Inoue

发明人： Tatsuhiko Fujihira ,  Takashi Kobayashi ,  Hitoshi Abe ,  Yasushi Niimura ,  Masanori Inoue

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L23/58

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical MOS semiconductor device exhibits a high breakdown voltage and low on-resistance, reduces the tradeoff relation between the on-resistance and the breakdown voltage, and realizes high speed switching. The semiconductor device has a breakdown-voltage sustaining layer, such as an n−-type drift layer, and a well region, such as a p-type well region, in the breakdown-voltage sustaining layer. The resistivity ρ (Ωcm) of the breakdown-voltage layer is within a range expressed in terms of the breakdown voltage Vbr (V). The semiconductor device also has stripe shaped surface drain regions that extend from the well region and are surrounded by the well region. The surface area ratio between surface drain regions and the well region, which includes the source region, is from 0.01 to 0.2.

摘要翻译： 垂直MOS半导体器件表现出高的击穿电压和低导通电阻，降低了导通电阻和击穿电压之间的折衷关系，实现了高速切换。 该半导体器件具有击穿电压维持层，例如n + P型漂移层，以及击穿电压维持层中的诸如p型阱区的阱区。 击穿电压层的电阻率rho（Ωgacm）在以击穿电压Vbr（V）表示的范围内。 半导体器件还具有从阱区域延伸并被阱区域包围的条形表面漏极区域。 表面漏区与包含源区的阱区的表面积比为0.01〜0.2。

公开(公告)号：US06894319B2

公开(公告)日：2005-05-17

申请号：US10020573

申请日：2001-10-31

申请人： Takashi Kobayashi ,  Tatsuhiko Fujihira ,  Hitoshi Abe ,  Yasushi Niimura ,  Masanori Inoue

发明人： Takashi Kobayashi ,  Tatsuhiko Fujihira ,  Hitoshi Abe ,  Yasushi Niimura ,  Masanori Inoue

IPC分类号： H01L23/29 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L23/293 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MOS semiconductor device includes n−-type surface regions, which are extended portions of an n−-type drift layer 12 extended to the surface of the semiconductor chip. Each n−-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n−-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 μm or less.

公开(公告)号：US06502888B2

公开(公告)日：2003-01-07

申请号：US09898654

申请日：2001-07-03

申请人： Masanori Inoue ,  Koichi Fujita ,  Koji Saitoh ,  Shoji Abe

发明人： Masanori Inoue ,  Koichi Fujita ,  Koji Saitoh ,  Shoji Abe

IPC分类号： B62D2514

CPC分类号： B60K37/00 ,  B60K2350/943

摘要： In an instrument panel arrangement, a first permanent fixture is attached a second permanent fixture via a latch mechanism including a latch member engaging the first permanent fixture to the second permanent fixture and a handle member for selectively disengaging the latch member. The latch system allows the first and second permanent fixtures to be installed and removed in a simple manner, and this not only simplifies the assembly and maintenance work, but also facilitates the work in separating component parts for recycling when discarding or scrapping the automobile.

公开(公告)号：US20100009551A1

公开(公告)日：2010-01-14

申请号：US12565461

申请日：2009-09-23

申请人： Masanori INOUE

发明人： Masanori INOUE

IPC分类号： H01L21/26

CPC分类号： H01L21/263 ,  H01L29/32 ,  H01L29/66136 ,  H01L29/861

摘要： A p-n junction is formed at the interface of a low-concentration n-type impurity layer and a p-type diffusion region in the vicinity of the upper major surface of an n-type semiconductor substrate of a semiconductor device. A mask composed of an absorber is placed on the upper major surface of the semiconductor device, and electron beams are radiated. Thereafter, heat treatment is conducted. As a result, the peak of the crystal lattice defect densities is present in the vicinity of the upper major surface of the n-type semiconductor substrate, and the crystal lattice defect densities are decreasingly distributed toward the lower major surface. Thereby, a semiconductor device that can minimize the variation of the breakdown voltage characteristics of the p-n junction of the diode, and can control the optimum carrier lifetime can be obtained.

摘要翻译： 在半导体器件的n型半导体衬底的上主表面附近的低浓度n型杂质层和p型扩散区的界面处形成p-n结。 将由吸收体构成的掩模放置在半导体器件的上主表面上，并且辐射电子束。 之后，进行热处理。 结果，在n型半导体衬底的上主表面附近存在晶格缺陷密度的峰值，并且晶格缺陷密度朝着下主表面逐渐分布。 由此，可以获得能够最小化二极管的p-n结的击穿电压特性的变化并能够控制最佳载流子寿命的半导体器件。

公开(公告)号：US5526214A

公开(公告)日：1996-06-11

申请号：US127609

申请日：1993-09-28

申请人： Ikunori Takata ,  Masanori Inoue

发明人： Ikunori Takata ,  Masanori Inoue

IPC分类号： H01L29/73 ,  H01L21/331 ,  H03K17/08 ,  H03K17/082 ,  H03K17/615 ,  H02H7/20 ,  H02H9/04

CPC分类号： H03K17/0826 ,  H03K17/615

摘要： The present invention is directed to effectively prevent "load short-circuit breakdown" of a power Darlington transistor. When a potential different between a base BX and emitter E at a final stage of a power Darlington transistor (20) is at a specified level of voltage determined by base-emitter forward voltage of a protective bipolar transistor (32), the protective bipolar transistor (32) turns on, and accordingly, base current I.sub.B at an initial stage of the power Darlington transistor (20) is bypassed to the emitter E at the final stage. Hence, excessive rising of collector current I.sub.C of the Darlington transistor (20) is suppressed, and "load short-circuit breakdown" is prevented. The potential difference does not depend upon the number of stages of the Darlington transistor nor temperature, and therefore, it is facilitated for Darlington transistors of various numbers of stages to design a short-circuit protective circuit to ensure a specified bypass operation in the whole range of working temperature.

摘要翻译： 本发明旨在有效地防止功率达林顿晶体管的“负载短路故障”。 当功率达林顿晶体管（20）的最后级的基极BX和发射极E之间的电位处于由保护双极晶体管（32）的基极 - 发射极正向电压确定的电压的指定电平时，保护双极晶体管 （32）导通，因此，在最终阶段，在功率达林顿晶体管（20）的初始阶段的基极电流IB被旁路到发射极E. 因此，抑制了达林顿晶体管（20）的集电极电流IC的过度上升，并且防止了“负载短路击穿”。 电位差不取决于达林顿晶体管的级数和温度，因此，为各种级数的达林顿晶体管设计短路保护电路，以便在整个范围内确保指定的旁路工作， 的工作温度。

公开(公告)号：US06989535B2

公开(公告)日：2006-01-24

申请号：US10309278

申请日：2002-12-04

申请人： Hiroshi Tani ,  Yoko Ogawa ,  Masanori Inoue ,  Takaaki Shirakura ,  Koji Sonoda

发明人： Hiroshi Tani ,  Yoko Ogawa ,  Masanori Inoue ,  Takaaki Shirakura ,  Koji Sonoda

IPC分类号： G01N23/00

CPC分类号： G01Q60/38 ,  G11B5/8408 ,  Y10S977/852

摘要： To provide an atomic force microscopy which allows the measurement of the configuration of a surface being measured by using the phenomenon observed between the surface being measured and a probe approaching thereto at very fine distance.By selecting the material of the tip surface of said probe such that the surface energy of said probe tip becomes less than the interface energy between the tip surface and the surface being measured, thereby the surface configuration of soft body, or soft fouling adhered to the body surface can be measured.A method of measuring the surface configuration and a method of producing magnetic recording medium using the same are also provided.