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    Static random access memory
    2.
    发明授权
    Static random access memory 失效
    静态随机存取存储器

    公开(公告)号：US5936909A

    公开(公告)日：1999-08-10

    申请号：US13911

    申请日：1998-01-27

    申请人： Takahiro Sonoda ,  Sadayuki Morita ,  Hirofumi Zushi ,  Haruko Kawachino ,  Hideharu Yahata ,  Kenichi Fukui ,  Tomohiro Nagano ,  Masashige Harada

    发明人： Takahiro Sonoda ,  Sadayuki Morita ,  Hirofumi Zushi ,  Haruko Kawachino ,  Hideharu Yahata ,  Kenichi Fukui ,  Tomohiro Nagano ,  Masashige Harada

    IPC分类号： G11C7/10 ,  G11C11/418 ,  G11C7/00

    CPC分类号： G11C7/1072 ,  G11C11/418 ,  G11C7/1018

    摘要： A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address selection circuit selects a memory cell in one of the memory mats, and connects the selected memory cell to a sense amplifier or a write amplifier furnished corresponding to the memory mat in question. At the same time, an address counter generates an address signal corresponding to the address signal by which one of the memory mats has been selected. When a burst mode is designated by a control signal, the address signal admitted to the address register is used to select a memory cell in a first memory mat. The selected memory cell is connected to the corresponding sense amplifier or write amplifier. Then in accordance with the address signal generated by the address counter, a memory cell in another memory mat is selected and connected to the corresponding sense amplifier or write amplifier.

    摘要翻译： 静态RAM具有多个存储器堆，每个存储器堆包括在多个字线和多个数据线之间的交点处以矩阵模式形成的多个静态存储器单元。 地址选择电路在接收到地址寄存器中的地址信号后，选择存储器垫之一中的存储单元，并将所选择的存储单元连接到与所讨论的存储器衬垫对应的读出放大器或写入放大器。 同时，地址计数器产生与已经选择了一个存储器垫的地址信号对应的地址信号。 当通过控制信号指定突发模式时，允许进入地址寄存器的地址信号用于选择第一存储器存储器中的存储器单元。 所选择的存储单元连接到相应的读出放大器或写放大器。 然后根据地址计数器产生的地址信号，选择另一个存储器存储器中的存储单元并将其连接到相应的读出放大器或写入放大器。

    Semiconductor integrated circuit with memory redundancy circuit
    5.
    发明申请
    Semiconductor integrated circuit with memory redundancy circuit 有权

    公开(公告)号：US20070286001A1

    公开(公告)日：2007-12-13

    申请号：US11783123

    申请日：2007-04-06

    申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    IPC分类号： G11C7/00

    CPC分类号： G06F11/1008 ,  G11C29/848

    摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

    Semiconductor integrated circuit with memory redundancy circuit
    6.
    发明授权
    Semiconductor integrated circuit with memory redundancy circuit 有权
    半导体集成电路与存储器冗余电路

    公开(公告)号：US07219272B2

    公开(公告)日：2007-05-15

    申请号：US10170583

    申请日：2002-06-14

    申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    IPC分类号： G11C29/00 ,  G06F11/00 ,  G11C7/00

    CPC分类号： G06F11/1008 ,  G11C29/848

    摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

    摘要翻译： 一种具有存储器冗余电路的半导体集成电路，用于解决由使用ECC电路进行纠错引起的增加的面积，功耗和访问时间的问题。 该电路包括：多个存储垫; 平行于字线的本地总线，其传送读取数据并从存储器单元写入数据; 与数据线并行的写入全局总线，其从输入焊盘IO传送写入数据; 用于读取数据线的全局总线，其将读取的数据传送到输出焊盘IO; 以及位于全局总线和本地总线的交叉点处的至少一个纠错电路。 读取和写入可以在单个周期中完成，并且在写入操作期间，写入与先前读取的数据不同的数据。 通过这种配置，可以避免面积和功耗的增加，并且可以校正诸如软错误的错误。

    Semiconductor memory cells with shared p-type well
    7.
    发明授权
    Semiconductor memory cells with shared p-type well 有权
    具有共享p型的半导体存储器单元

    公开(公告)号：US07710764B2

    公开(公告)日：2010-05-04

    申请号：US11783123

    申请日：2007-04-06

    申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    IPC分类号： G11C11/00

    CPC分类号： G06F11/1008 ,  G11C29/848

    摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit includes: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

    摘要翻译： 一种具有存储器冗余电路的半导体集成电路，用于解决由使用ECC电路进行纠错引起的增加的面积，功耗和访问时间的问题。 电路包括：多个存储垫; 平行于字线的本地总线，其传送读取数据并从存储器单元写入数据; 与数据线并行的写入全局总线，其从输入焊盘IO传送写入数据; 用于读取数据线的全局总线，其将读取的数据传送到输出焊盘IO; 以及位于全局总线和本地总线的交叉点处的至少一个纠错电路。 读取和写入可以在单个周期中完成，并且在写入操作期间，写入与先前读取的数据不同的数据。 通过这种配置，可以避免面积和功耗的增加，并且可以校正诸如软错误的错误。