公开(公告)号：US08503234B2

公开(公告)日：2013-08-06

申请号：US13188869

申请日：2011-07-22

申请人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

发明人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

IPC分类号： G11C16/04 ,  G11C16/06 ,  H01L29/792

CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

摘要翻译： 一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。 列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

公开(公告)号：US20120193711A1

公开(公告)日：2012-08-02

申请号：US13301698

申请日：2011-11-21

申请人： Masayoshi Asano ,  Junichi Mitani

发明人： Masayoshi Asano ,  Junichi Mitani

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/0262 ,  H01L27/0277 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66121 ,  H01L29/66393 ,  H01L29/66689 ,  H01L29/7436 ,  H01L29/7816 ,  H01L29/87

摘要： A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1≧A2 and B1

摘要翻译： 形成在ESD保护元件形成区域中的LDMOS晶体管形成区域中的栅极电极，元件隔离膜和漏极区域以及栅极电极，元件隔离膜和阳极区域，以满足A1≥A2和B1 < B2，其中LDMOS晶体管形成区域具有栅电极和元件隔离膜的重叠长度A1以及栅电极和漏区之间的距离B1，并且ESD保护元件形成区域具有栅电极的重叠长度A2 元件隔离膜和栅电极与阳极区之间的距离B2。

公开(公告)号：US20110280072A1

公开(公告)日：2011-11-17

申请号：US13188869

申请日：2011-07-22

申请人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

发明人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

IPC分类号： G11C16/08 ,  H01L29/788

CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

摘要翻译： 一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列译码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。 列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

公开(公告)号：US08012849B2

公开(公告)日：2011-09-06

申请号：US12815782

申请日：2010-06-15

申请人： Masayoshi Asano ,  Yoshiyuki Suzuki

发明人： Masayoshi Asano ,  Yoshiyuki Suzuki

IPC分类号： H01L21/76

CPC分类号： H01L27/10873 ,  H01L21/84 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/12 ,  H01L29/94

摘要： A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and a channel dose region is formed at the upper layer portion of the active region, and another channel stop region is formed immediately under the STI.

摘要翻译： 在STI的正下方形成通道停止区域，然后在有源区的上层部分掺杂有杂质的条件下进行离子注入，同时杂质也被立即掺杂 在另一个STI下方，并且在有源区的上层部分处形成沟道剂量区，并且在STI之下立即形成另一个沟道停止区。

公开(公告)号：US07928515B2

公开(公告)日：2011-04-19

申请号：US12136955

申请日：2008-06-11

申请人： Masayoshi Asano ,  Yoshiyuki Suzuki ,  Tetsuya Ito ,  Hajime Wada

发明人： Masayoshi Asano ,  Yoshiyuki Suzuki ,  Tetsuya Ito ,  Hajime Wada

IPC分类号： H01L29/00

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1052 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10894 ,  H01L29/945

摘要： A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.

摘要翻译： 一种半导体器件包括具有不同导电类型的栅电极和同一衬底上的沟槽电容器型存储器的双栅极CMOS逻辑电路，包括用于沟槽电容器的衬底的沟槽，形成在沟槽中的电介质膜，第一多晶硅 形成在沟槽内部的膜，以及位于电介质膜上方的电池板电极。 电池板电极包括形成在部分地填充沟槽的电介质膜上的第一多晶硅膜和形成在第一多晶硅膜上以完全填充沟槽的第二多晶硅膜。 第二多晶硅膜包括用于形成栅电极的足够的膜厚度，其中第一多晶硅膜的杂质浓度高于第二多晶硅膜的杂质浓度。

公开(公告)号：US08014198B2

公开(公告)日：2011-09-06

申请号：US12411938

申请日：2009-03-26

申请人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

发明人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

IPC分类号： G11C16/04 ,  G11C29/792 ,  G11C16/06

CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

摘要翻译： 一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。 列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

公开(公告)号：US20090180320A1

公开(公告)日：2009-07-16

申请号：US12411938

申请日：2009-03-26

申请人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

发明人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

IPC分类号： G11C16/04 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

摘要翻译： 一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。 列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

公开(公告)号：US20080001258A1

公开(公告)日：2008-01-03

申请号：US11589084

申请日：2006-10-30

申请人： Taiji Ema ,  Masayoshi Asano ,  Toru Anezaki ,  Junichi Ariyoshi

发明人： Taiji Ema ,  Masayoshi Asano ,  Toru Anezaki ,  Junichi Ariyoshi

IPC分类号： H01L29/00 ,  H01L31/0288 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823892 ,  H01L27/0921 ,  H01L27/11803

摘要： According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.

摘要翻译： 根据本发明，提供一种半导体器件，包括：p型硅衬底; 在硅衬底中形成浅的n阱; 在硅衬底中的浅n阱旁边形成浅的p阱; 以及在硅衬底中的浅p-阱旁边形成深深的n阱，并且比深p阱更深。 此外，在浅层p阱和硅衬底中的深n阱之间形成深浅的p阱，其深于浅的p阱。

公开(公告)号：US20070164339A1

公开(公告)日：2007-07-19

申请号：US11369845

申请日：2006-03-08

申请人： Masayoshi Asano ,  Yoshiyuki Suzuki

发明人： Masayoshi Asano ,  Yoshiyuki Suzuki

IPC分类号： H01L21/8242

CPC分类号： H01L27/10873 ,  H01L21/84 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/12 ,  H01L29/94

摘要： A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and a channel dose region is formed at the upper layer portion of the active region, and another channel stop region is formed immediately under the STI.

摘要翻译： 在STI的正下方形成通道停止区域，然后在有源区的上层部分掺杂有杂质的条件下进行离子注入，同时杂质也被立即掺杂 在另一个STI下方，并且在有源区的上层部分处形成沟道剂量区，并且在STI之下立即形成另一个沟道停止区。

公开(公告)号：US08785274B2

公开(公告)日：2014-07-22

申请号：US12785964

申请日：2010-05-24

申请人： Katsuyoshi Matsuura ,  Masayoshi Asano ,  Hiroyuki Ogawa ,  Myounggoo Lee

发明人： Katsuyoshi Matsuura ,  Masayoshi Asano ,  Hiroyuki Ogawa ,  Myounggoo Lee

IPC分类号： H01L21/8242

CPC分类号： H01L29/66659 ,  H01L27/1085 ,  H01L27/10861 ,  H01L27/10894 ,  H01L28/91 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/7835

摘要： A method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a first region of a first electrical conduction type as a part of a surface layer of the semiconductor substrate and a first gate electrode and a capacitor structure, the first gate electrode and the capacitor structure being disposed on the first region; forming a first insulating film covering the first gate electrode and the capacitor structure, the first insulating film being covering the surface of the semiconductor substrate; implanting a first impurity of a second electrical conduction type into the semiconductor substrate, so as to form a region of the second electrical conduction type in each of a second region and a third region, the second region being a region between the first gate electrode and the capacitor structure, the third region being a region opposite to the capacitor structure with the first gate electrode therebetween.

摘要翻译： 一种制造半导体器件的方法包括制备具有第一导电类型的第一区域作为半导体衬底的表面层的一部分的半导体衬底和第一栅电极和电容器结构，第一栅电极和电容器 结构设置在第一区域上; 形成覆盖所述第一栅电极和所述电容器结构的第一绝缘膜，所述第一绝缘膜覆盖所述半导体基板的表面; 将第二导电类型的第一杂质注入到所述半导体衬底中，以便在第二区域和第三区域中的每一个中形成所述第二导电类型的区域，所述第二区域是所述第一栅电极和 电容器结构，第三区域是与电容器结构相反的区域，其间具有第一栅电极。