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公开(公告)号：US20130156133A1
公开(公告)日：2013-06-20
申请号：US12990721
申请日：2010-09-08
IPC分类号： H04L25/02
CPC分类号： H04L25/02 , H03M13/1111 , H03M13/1114 , H03M13/1117 , H03M13/1137 , H03M13/114 , H03M13/2957 , H03M13/2972 , H03M13/3905 , H03M13/3972 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6527 , H03M13/653 , H03M13/6541 , H03M13/6544 , H03M13/6552 , H03M13/6555 , H03M13/6566 , H03M13/6569
摘要： A configurable Turbo-LDPC decoder comprising: A set of P>1 Soft-Input-Soft-Output decoding units (DP0-DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of said decoding units having first (I1i) and second (I2i) input ports and first (O1i) and second (O2i) output ports for intermediate data; First and second memories (M1, M2) for storing said intermediate data, each of said first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of said decoding units to the output and input ports of said first memory, and the second input and output ports of said decoding units to the output and input ports of said second memory.
摘要翻译： 一种可配置的Turbo-LDPC解码器，包括：用于对Turbo和LDPC编码的输入数据进行迭代解码的一组P> 1个软输入软输出解码单元（DP0-DPP-1; DPi），每个所述解码单元 具有用于中间数据的第一（I1i）和第二（I2i）输入端口和第一（O1i）和第二（O2i）输出端口; 用于存储所述中间数据的第一和第二存储器（M1，M2），所述第一和第二存储器中的每一个包括具有相应输入和输出端口的P个独立可读和可写存储块; 以及用于将所述解码单元的第一输入和输出端口连接到所述第一存储器的输出和输入端口以及所述解码单元的第二输入和输出端口连接到所述第一存储器的输出端口和输入端口的可配置交换网络（SN） 第二个记忆
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2.发明申请Methods and architectures for layered decoding of LDPC codes with minimum latency 有权用于以最小延迟对LDPC码进行分层解码的方法和体系结构公开(公告)号：US20090063931A1
公开(公告)日：2009-03-05
申请号：US11897021
申请日：2007-08-27
申请人： Massimo Rovini , Francesco Rossi , Luca Fanucci
发明人： Massimo Rovini , Francesco Rossi , Luca Fanucci
IPC分类号： G06F11/10
CPC分类号： H03M13/1137 , H03M13/114
摘要： An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition of input data for a next layer, whereby the current layer and the next layer may attempt to use soft output information common to both layers. The serial processing unit is configured for delaying acquisition of input data for the next layer over a number of idle clock cycles. Latency due to the idle clock cycles is minimized by selectively modifying the sequence of layers through the decoding process and the sequence of messages processed by a certain layer.
摘要翻译： 用于解码低密度奇偶校验编码输入数据的解码器的实施例包括以时钟周期工作的串行处理单元，以执行代码中的层的串行更新。 用于产生当前层的输出数据的串行处理单元的操作通过获取下一层的输入数据进行流水线化，由此当前层和下一层可以尝试使用两层共同的软输出信息。 串行处理单元被配置为在多个空闲时钟周期内延迟对下一层的输入数据的采集。 通过选择性地通过解码过程和由某一层处理的消息序列来选择性地修改层序列，由于空闲时钟周期的延迟被最小化。
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3.发明授权公开(公告)号：US07359428B2
公开(公告)日：2008-04-15
申请号：US10901976
申请日：2004-07-30
申请人： Massimo Rovini , Giovanni Vanini , Luca Fanucci
发明人： Massimo Rovini , Giovanni Vanini , Luca Fanucci
IPC分类号： H04B1/707
摘要： An improved transmission method for high-rate digital communication on unshielded twisted copper pairs for Very-High Speed Digital Subscriber Loop (VDSL) modems. The new modulation scheme is a Multi Code Multi Carrier Code Division Multiple Access, hereafter named MC2 CDMA. The system takes advantage from both the CDMA modulation and the Multi-Carrier transmission and, in addition, the channel throughput is increased adopting a multi-code approach. The novel scheme encompasses transmitter, channel and receiver loading.
摘要翻译： 一种用于超高速数字用户环路（VDSL）调制解调器的非屏蔽双绞线对的高速数字通信的改进传输方法。 新的调制方案是多码多载波码分多址，以下称为MC <2> CDMA。 该系统利用CDMA调制和多载波传输两者，此外，采用多码方式增加了信道吞吐量。 新颖的方案包括发射机，信道和接收机加载。
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公开(公告)号：US08879670B2
公开(公告)日：2014-11-04
申请号：US12990721
申请日：2010-09-08
IPC分类号： H04L27/06
CPC分类号： H04L25/02 , H03M13/1111 , H03M13/1114 , H03M13/1117 , H03M13/1137 , H03M13/114 , H03M13/2957 , H03M13/2972 , H03M13/3905 , H03M13/3972 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6527 , H03M13/653 , H03M13/6541 , H03M13/6544 , H03M13/6552 , H03M13/6555 , H03M13/6566 , H03M13/6569
摘要： A configurable Turbo-LDPC decoder having A set of P>1 Soft-Input-Soft-Output decoding units (DP0-DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of the decoding units having first (I1i) and second (I2i) input ports and first (O1i) and second (O2i) output ports for intermediate data; First and second memories (M1, M2) for storing the intermediate data, each of the first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of the decoding units to the output and input ports of the first memory, and the second input and output ports of the decoding units to the output and input ports of the second memory.
摘要翻译： 一种可配置的Turbo-LDPC解码器，其具有用于迭代地解码Turbo和LDPC编码的输入数据的P> 1个软输入 - 软输出解码单元（DP0-DPP-1; DPi）集合，每个解码单元具有 用于中间数据的第一（I1i）和第二（I2i）输入端口和第一（O1i）和第二（O2i）输出端口; 用于存储中间数据的第一和第二存储器（M1，M2），第一和第二存储器中的每一个包括具有相应输入和输出端口的P个独立可读和可写存储块; 和可配置交换网络（SN），用于将解码单元的第一输入和输出端口连接到第一存储器的输出和输入端口，以及将解码单元的第二输入和输出端口连接到第一存储器的输出和输入端口 第二个记忆
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公开(公告)号：US20050102597A1
公开(公告)日：2005-05-12
申请号：US10926063
申请日：2004-08-26
申请人： Alfonso Martinez , Massimo Rovini
发明人： Alfonso Martinez , Massimo Rovini
CPC分类号： H04L1/0051 , H03M13/2978 , H03M13/2987 , H03M13/6561 , H04L1/0066
摘要： Iterative decoder comprising a plurality of servers which perform the iterative decoding of a data block each, an input buffer memory and a control unit which performs a statistical multiplexing of the data at input, which are firstly stored in the input buffer memory and successively processed by one of the servers. The input buffer memory comprises N+L memory locations, where N is the number of servers and L is the number of so-called additional locations. Each block to be decoded which is received while all the servers are busy is stored in one of the L additional locations possibly available, or it is lost if the input buffer memory is entirely filled. The number L of additional locations and the number N of servers are such that the probability PB of a block being lost, calculated on the basis of a queuing model of D/G/N/N+L type, satisfies the condition PB≦α·FER*, where FER* is the error rate in the blocks allowed and α
摘要翻译： 迭代解码器包括执行数据块的迭代解码的多个服务器，输入缓冲存储器和执行输入的数据的统计多路复用的控制单元，其首先存储在输入缓冲存储器中并由 其中一个服务器。 输入缓冲存储器包括N + L个存储器位置，其中N是服务器的数量，L是所谓的附加位置的数量。 在所有服务器忙时接收的每个待解码的块被存储在可能可用的L个附加位置中的一个中，或者如果输入缓冲存储器被完全填满则丢失。 附加位置的数量L和服务器的数量N使得根据D / G / N / N + L的排队模型计算出的丢失块的概率P SUB B
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6.发明授权Methods and architectures for layered decoding of LDPC codes with minimum latency 有权用于以最小延迟对LDPC码进行分层解码的方法和体系结构公开(公告)号：US08181083B2
公开(公告)日：2012-05-15
申请号：US11897021
申请日：2007-08-27
申请人： Massimo Rovini , Francesco Rossi , Luca Fanucci
发明人： Massimo Rovini , Francesco Rossi , Luca Fanucci
IPC分类号： G06F11/10
CPC分类号： H03M13/1137 , H03M13/114
摘要： An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition of input data for a next layer, whereby the current layer and the next layer may attempt to use soft output information common to both layers. The serial processing unit is configured for delaying acquisition of input data for the next layer over a number of idle clock cycles. Latency due to the idle clock cycles is minimized by selectively modifying the sequence of layers through the decoding process and the sequence of messages processed by a certain layer.
摘要翻译： 用于解码低密度奇偶校验编码输入数据的解码器的实施例包括以时钟周期工作的串行处理单元，以执行代码中的层的串行更新。 用于产生当前层的输出数据的串行处理单元的操作通过获取下一层的输入数据进行流水线化，由此当前层和下一层可以尝试使用两层共同的软输出信息。 串行处理单元被配置为在多个空闲时钟周期内延迟对下一层的输入数据的采集。 通过选择性地通过解码过程和由某一层处理的消息序列来选择性地修改层序列，由于空闲时钟周期的延迟被最小化。
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公开(公告)号：US07275203B2
公开(公告)日：2007-09-25
申请号：US10926063
申请日：2004-08-26
申请人： Alfonso Martinez , Massimo Rovini
发明人： Alfonso Martinez , Massimo Rovini
IPC分类号： H03M13/03
CPC分类号： H04L1/0051 , H03M13/2978 , H03M13/2987 , H03M13/6561 , H04L1/0066
摘要： Iterative decoder comprising a plurality of servers which perform the iterative decoding of a data block each, an input buffer memory and a control unit which performs a statistical multiplexing of the data at input, which are firstly stored in the input buffer memory and successively processed by one of the servers. The input buffer memory comprises N+L memory locations, where N is the number of servers and L is the number of so-called additional locations. Each block to be decoded which is received while all the servers are busy is stored in one of the L additional locations possibly available, or it is lost if the input buffer memory is entirely filled. The number L of additional locations and the number N of servers are such that the probability PB of a block being lost, calculated on the basis of a queuing model of D/G/N/N+L type, satisfies the condition PB≦α·FER*, where FER* is the error rate in the blocks allowed and α
摘要翻译： 迭代解码器包括执行数据块的迭代解码的多个服务器，输入缓冲存储器和执行输入的数据的统计多路复用的控制单元，其首先存储在输入缓冲存储器中并由 其中一个服务器。 输入缓冲存储器包括N + L个存储器位置，其中N是服务器的数量，L是所谓的附加位置的数量。 在所有服务器忙时接收的每个待解码的块被存储在可能可用的L个附加位置中的一个中，或者如果输入缓冲存储器被完全填满则丢失。 附加位置的数量L和服务器的数量N使得根据D / G / N / N + L的排队模型计算出的丢失块的概率P SUB B
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8.发明申请公开(公告)号：US20050002441A1
公开(公告)日：2005-01-06
申请号：US10901976
申请日：2004-07-30
申请人： Massimo Rovini , Giovanni Vanini , Luca Fanucci
发明人： Massimo Rovini , Giovanni Vanini , Luca Fanucci
摘要： An improved transmission method for high-rate digital communication on unshielded twisted copper pairs for Very-High Speed Digital Subscriber Loop (VDSL) modems. The new modulation scheme is a Multi Code Multi Carrier Code Division Multiple Access, hereafter named MC2 CDMA. The system takes advantage from both the CDMA modulation and the Multi-Carrier transmission and, in addition, the channel throughput is increased adopting a multi-code approach. The novel scheme encompasses transmitter, channel and receiver. loading.
摘要翻译： 一种用于超高速数字用户环路（VDSL）调制解调器的非屏蔽双绞线对的高速数字通信的改进传输方法。 新的调制方案是多码多载波码分多址，以下称为MC <2> CDMA。 该系统利用CDMA调制和多载波传输两者，此外，采用多码方式增加了信道吞吐量。 新颖的方案包括发射机，信道和接收机。 加载。
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