公开(公告)号：US20130026612A1

公开(公告)日：2013-01-31

申请号：US13194033

申请日：2011-07-29

Applicant: Hsiang-Tai LU ,  Chih-Hsien LIN ,  Meng-Lin CHUNG

Inventor： Hsiang-Tai LU ,  Chih-Hsien LIN ,  Meng-Lin CHUNG

IPC: H01L23/552 ,  H01L21/265

CPC classification number: H01L21/265 ,  H01L21/76802 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/552 ,  H01L2224/16

Abstract: A passive interposer apparatus with a shielded through silicon via (TSV) configuration is disclosed. The apparatus includes a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped. An interlayer dielectric layer (ILD) is disposed over the upper portion of the p-doped substrate. A plurality of through silicon vias (TSVs) are formed through the ILD and the p-doped substrate. A plurality of shielding lines disposed between the TSVs electrically couple respective second metal contact pads to the upper portion of the p-doped substrate.

Abstract translation: 公开了一种具有屏蔽硅通孔（TSV）配置的无源中介器。 该装置包括p掺杂衬底，其中至少p掺杂衬底的上部是高度p掺杂的。 层间电介质层（ILD）设置在p掺杂衬底的上部上。 通过ILD和p掺杂衬底形成多个穿通硅通孔（TSV）。 设置在TSV之间的多个屏蔽线将各个第二金属接触焊盘电耦合到p掺杂衬底的上部。

公开(公告)号：US20130007692A1

公开(公告)日：2013-01-03

申请号：US13172248

申请日：2011-06-29

Applicant: Chao-Yang Yeh ,  Ze-Ming Wu ,  Meng-Lin Chung ,  Chih-Chia Chen ,  Li-Fu Ding ,  Sa-Lly Liu

Inventor： Chao-Yang Yeh ,  Ze-Ming Wu ,  Meng-Lin Chung ,  Chih-Chia Chen ,  Li-Fu Ding ,  Sa-Lly Liu

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium.

Abstract translation: 一种方法包括使用机器实施的RC提取工具来分析半导体插入器上的前侧导电图案和背面导电图案，并将表示多个相应RC节点的数据从RC提取工具输出到有形的持久机器可读存储介质。 产生半导体插入器的衬底网格模型，其具有多个衬底网格节点。 每个衬底网格节点通过相应的衬底阻抗元件连接到多个衬底网格节点中的相邻衬底网格节点。 形成了一组时序分析工具的输入。 多个RC节点连接到衬底网格模型的多个衬底网格节点中的一个。 该组输入存储在有形机器可读存储介质中。

公开(公告)号：US08269350B1

公开(公告)日：2012-09-18

申请号：US13149480

申请日：2011-05-31

Applicant: Chih-Chia Chen ,  Chao-Yang Yeh ,  Meng-Lin Chung

Inventor： Chih-Chia Chen ,  Chao-Yang Yeh ,  Meng-Lin Chung

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/485

CPC classification number: H01L23/49827 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L2223/6622 ,  H01L2224/131 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/014

Abstract: An interconnection component includes a plurality of through-substrate vias (TSVs) penetrating through a substrate. The plurality of TSVs includes an active TSV having a first end and a second end. The first end of the active TSV is electrically coupled to a signal-providing circuit. The second end of the active TSV is electrically coupled to an additional package component bonded to the interconnection component. The plurality of TSVs further includes a dummy TSV having a first end and a second end, wherein the first end is electrically coupled to the signal-providing circuit, and wherein the second end is open ended.

Abstract translation: 互连部件包括贯穿基板的多个穿通基板通路（TSV）。 多个TSV包括具有第一端和第二端的有源TSV。 有源TSV的第一端电耦合到信号提供电路。 有源TSV的第二端电耦合到结合到互连部件的附加封装部件。 多个TSV还包括具有第一端和第二端的虚拟TSV，其中第一端电耦合到信号提供电路，并且其中第二端是开放式的。

公开(公告)号：US08856710B2

公开(公告)日：2014-10-07

申请号：US13172248

申请日：2011-06-29

Applicant: Chao-Yang Yeh ,  Ze-Ming Wu ,  Meng-Lin Chung ,  Chih-Chia Chen ,  Li-Fu Ding ,  Sa-Lly Liu

Inventor： Chao-Yang Yeh ,  Ze-Ming Wu ,  Meng-Lin Chung ,  Chih-Chia Chen ,  Li-Fu Ding ,  Sa-Lly Liu

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium.

Abstract translation: 一种方法包括使用机器实施的RC提取工具来分析半导体插入器上的前侧导电图案和背面导电图案，并将表示多个相应RC节点的数据从RC提取工具输出到有形的持久机器可读存储介质。 产生半导体插入器的衬底网格模型，其具有多个衬底网格节点。 每个衬底网格节点通过相应的衬底阻抗元件连接到多个衬底网格节点中的相邻衬底网格节点。 形成了一组时序分析工具的输入。 多个RC节点连接到衬底网格模型的多个衬底网格节点中的一个。 该组输入存储在有形机器可读存储介质中。

公开(公告)号：US08618640B2

公开(公告)日：2013-12-31

申请号：US13194033

申请日：2011-07-29

Applicant: Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Meng-Lin Chung

Inventor： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Meng-Lin Chung

IPC: H01L23/552

CPC classification number: H01L21/265 ,  H01L21/76802 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/552 ,  H01L2224/16

Abstract: A passive interposer apparatus with a shielded through silicon via (TSV) configuration is disclosed. The apparatus includes a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped. An interlayer dielectric layer (ILD) is disposed over the upper portion of the p-doped substrate. A plurality of through silicon vias (TSVs) are formed through the ILD and the p-doped substrate. A plurality of shielding lines disposed between the TSVs electrically couple respective second metal contact pads to the upper portion of the p-doped substrate.

Abstract translation: 公开了一种具有屏蔽硅通孔（TSV）配置的无源中介器。 该装置包括p掺杂衬底，其中至少p掺杂衬底的上部是高度p掺杂的。 层间电介质层（ILD）设置在p掺杂衬底的上部上。 通过ILD和p掺杂衬底形成多个穿通硅通孔（TSV）。 设置在TSV之间的多个屏蔽线将各个第二金属接触焊盘电耦合到p掺杂衬底的上部。