公开(公告)号：US09230849B2

公开(公告)日：2016-01-05

申请号：US13825079

申请日：2012-09-25

申请人： Zengfeng Di ,  Da Chen ,  Jiantao Bian ,  Zhongying Xue ,  Miao Zhang

发明人： Zengfeng Di ,  Da Chen ,  Jiantao Bian ,  Zhongying Xue ,  Miao Zhang

IPC分类号： H01L21/30 ,  H01L21/762 ,  H01L21/306

CPC分类号： H01L21/76254 ,  H01L21/30604 ,  H01L21/30625

摘要： The present invention provides a method for preparing an ultra-thin material on insulator through adsorption by a doped ultra-thin layer. In the method, first, an ultra-thin doped single crystal film and an ultra-thin top film (or contains a buffer layer) are successively and epitaxially grown on a first substrate, and then a high-quality ultra-thin material on insulator is prepared through ion implantation and a bonding process. A thickness of the prepared ultra-thin material on insulator ranges from 5 nm to 50 nm. In the present invention, the ultra-thin doped single crystal film adsorbs the implanted ion, and a micro crack is then formed, so as to implement ion-cut; therefore, the roughness of a surface of a ion-cut material on insulator is small. In addition, an impurity atom strengthens an ion adsorption capability of the ultra-thin single crystal film, so that an ion implantation dose and the annealing temperature can be lowered in the preparation procedure, thereby effectively reducing the damage caused by the implantation to the top film, and achieving objectives of improving production efficiency and reducing the production cost.

摘要翻译： 本发明提供一种通过掺杂超薄层吸附制备绝缘体上的超薄材料的方法。 在该方法中，首先，在第一基板上依次外延生长超薄掺杂单晶膜和超薄顶膜（或包含缓冲层），然后在绝缘体上形成高品质超薄材料 通过离子注入和粘合工艺制备。 所制备的绝缘体上的超薄材料的厚度范围为5nm至50nm。 在本发明中，超薄掺杂单晶膜吸附注入的离子，然后形成微裂纹，从而实现离子切割; 因此，绝缘体上的离子切割材料的表面的粗糙度小。 此外，杂质原子增强了超薄单晶膜的离子吸附能力，使得在制备过程中可以降低离子注入剂量和退火温度，从而有效地减少了植入到顶部的损伤 电影，实现提高生产效率和降低生产成本的目标。

公开(公告)号：US08633090B2

公开(公告)日：2014-01-21

申请号：US13383416

申请日：2010-07-10

申请人： Xiang Wang ,  Xing Wei ,  Miao Zhang ,  Chenglu Lin ,  Xi Wang

发明人： Xiang Wang ,  Xing Wei ,  Miao Zhang ,  Chenglu Lin ,  Xi Wang

IPC分类号： H01L21/762

CPC分类号： H01L21/76256

摘要： A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.

摘要翻译： 提供一种形成具有掩埋绝缘层的边缘倒角衬底的方法，包括以下步骤：提供第一衬底（S10）; 在所述第一基板的表面上形成蚀刻掩模层，其中所述蚀刻掩模层形成在所述第一基板的整个表面上; 通过边缘磨削倒角第一基板的玻璃表面和其上的蚀刻掩模层（S12）; 通过旋转蚀刻，蚀刻通过边缘研磨而暴露在蚀刻掩模层上的第一衬底（S13）; 提供第二基板（S14）; 以及用掩埋绝缘层将第一衬底接合到第二衬底（S15）。 该方法避免了边缘崩溃和后续过程中翘曲度的变化。

公开(公告)号：US20140004684A1

公开(公告)日：2014-01-02

申请号：US13825010

申请日：2012-09-25

申请人： Zengfeng Di ,  Lin Ye ,  Zhongying Xue ,  Miao Zhang

发明人： Zengfeng Di ,  Lin Ye ,  Zhongying Xue ,  Miao Zhang

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a Smart-Cut technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.

摘要翻译： 本发明提供了一种制备GOI芯片结构的方法，其中在该方法中，首先通过使用Smart-Cut技术制造绝缘体上的SiGe（SGOI）芯片结构，然后在 SGOI芯片结构，从而获得GOI芯片结构。 由于采用智能切割技术制成的SGOI基本上在SGOI / BOX接口中没有错配位错，因此GOI的穿透位错密度最终降低。 本发明的技术简单，可以实现高质量的GOI芯片结构，并且锗冷凝技术得到极大改善。 离子注入技术和退火技术在目前的半导体工业中是相当成熟的技术，因此这种制备方法大大提高了半导体工业中锗浓缩技术的广泛应用的可能性。

公开(公告)号：US08501577B2

公开(公告)日：2013-08-06

申请号：US13636126

申请日：2012-05-16

申请人： Jiantao Bian ,  Zengfeng Di ,  Miao Zhang

发明人： Jiantao Bian ,  Zengfeng Di ,  Miao Zhang

IPC分类号： H01L21/76

CPC分类号： H01L21/84 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878

摘要： A preparation method for a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations and a preparation method of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) based on the method are disclosed. In the preparation method for the full-isolated SOI substrate with hybrid crystal orientations provided in the present invention, a SiGe layer is adopted to serve as an epitaxial virtual substrate layer with a first crystal orientation, so as to form a strained top silicon with the first crystal orientation; a polysilicon supporting material is adopted to serve as a support for connecting the top silicon with the first crystal orientation and a top silicon with a second crystal orientation, so that the SiGe layer below the strained top silicon with the first crystal orientation may be removed, and an insulating material is filled to form an insulating buried layer. The top silicon and the insulating buried layer formed in the method have uniform and controllable thickness, the strained silicon formed in the window and the top silicon outside the window have different crystal orientations, so as to provide higher mobility for the NMOS and the PMOS respectively, thereby improving the performance of the CMOS IC.

摘要翻译： 公开了一种基于该方法的具有杂化晶体取向的完全隔离绝缘体（SOI）衬底的制备方法以及互补金属氧化物半导体（CMOS）集成电路（IC）的制备方法。 在本发明中提供的具有混合晶体取向的全隔离SOI衬底的制备方法中，采用SiGe层作为具有第一晶体取向的外延虚拟衬底层，以形成应变顶部硅，其中 第一个晶体取向; 采用多晶硅支撑材料作为连接顶部硅与第一晶体取向的支撑体和具有第二晶体取向的顶部硅，从而可以除去具有第一晶体取向的应变顶部硅以下的SiGe层， 并且填充绝缘材料以形成绝缘掩埋层。 在该方法中形成的顶部硅和绝缘掩埋层具有均匀且可控的厚度，窗口中形成的应变硅和窗外的顶部硅分别具有不同的晶体取向，从而为NMOS和PMOS分别提供更高的迁移率 ，从而提高CMOS IC的性能。

公开(公告)号：US08461651B2

公开(公告)日：2013-06-11

申请号：US13002303

申请日：2010-12-16

申请人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

发明人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L29/00

CPC分类号： H01L21/84 ,  H01L27/0255 ,  H01L27/1203

摘要： The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.

摘要翻译： 本发明公开了一种SOI CMOS电路中的ESD保护结构。 ESD保护结构包括各种纵向（垂直）PN结结构，其具有用于电流的显着扩大的接合面积。 所得到的装置实现了增加的大电流释放能力。 还公开了制造ESD保护纵向PN结的品种的工艺。 所公开的制造工艺与当前SOI技术的兼容性降低了实施成本并提高了集成度。

公开(公告)号：US20130071993A1

公开(公告)日：2013-03-21

申请号：US13636126

申请日：2012-05-16

申请人： Jiantao Bian ,  Zengfeng Di ,  Miao Zhang

发明人： Jiantao Bian ,  Zengfeng Di ,  Miao Zhang

IPC分类号： H01L21/76

CPC分类号： H01L21/84 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878

摘要： A preparation method for a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations and a preparation method of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) based on the method are disclosed. In the preparation method for the full-isolated SOI substrate with hybrid crystal orientations provided in the present invention, a SiGe layer is adopted to serve as an epitaxial virtual substrate layer with a first crystal orientation, so as to form a strained top silicon with the first crystal orientation; a polysilicon supporting material is adopted to serve as a support for connecting the top silicon with the first crystal orientation and a top silicon with a second crystal orientation, so that the SiGe layer below the strained top silicon with the first crystal orientation may be removed, and an insulating material is filled to form an insulating buried layer. The top silicon and the insulating buried layer formed in the method have uniform and controllable thickness, the strained silicon formed in the window and the top silicon outside the window have different crystal orientations, so as to provide higher mobility for the NMOS and the PMOS respectively, thereby improving the performance of the CMOS IC.

摘要翻译： 公开了一种基于该方法的具有杂化晶体取向的完全隔离绝缘体（SOI）衬底的制备方法和基于该互补金属氧化物半导体（CMOS）集成电路（IC）的制备方法。 在本发明中提供的具有混合晶体取向的全隔离SOI衬底的制备方法中，采用SiGe层作为具有第一晶体取向的外延虚拟衬底层，以形成应变顶部硅，其中 第一个晶体取向; 采用多晶硅支撑材料作为连接顶部硅与第一晶体取向的支撑体和具有第二晶体取向的顶部硅，从而可以除去具有第一晶体取向的应变顶部硅以下的SiGe层， 并且填充绝缘材料以形成绝缘掩埋层。 在该方法中形成的顶部硅和绝缘掩埋层具有均匀且可控的厚度，窗口中形成的应变硅和窗外的顶部硅分别具有不同的晶体取向，从而为NMOS和PMOS分别提供更高的迁移率 ，从而提高CMOS IC的性能。

公开(公告)号：US20130062696A1

公开(公告)日：2013-03-14

申请号：US13636128

申请日：2012-05-16

申请人： Zengfeng Di ,  Jiantao Bian ,  Miao Zhang ,  Xi Wang

发明人： Zengfeng Di ,  Jiantao Bian ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L27/12 ,  H01L21/20 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/8258

摘要： The present invention provides an SOI semiconductor structure with a hybrid of coplanar germanium (Ge) and III-V, and a method for preparing the same. A heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar on an insulator includes at least one Ge substrate formed on the insulating layer, and the other substrate is a group III-V semiconductor material formed on the Ge semiconductor. The preparation method for forming the semiconductor structure includes: preparing a global Ge on insulator substrate structure; preparing a group III-V semiconductor material layer on the Ge on insulator substrate structure; performing photolithography and etching for the first time to make a patterned window to the above of a Ge layer to form a recess; preparing a spacer in the recess; preparing a Ge film by selective epitaxial growth; performing a chemical mechanical polishing to obtain the heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material being coplanar; removing the spacer and a defective Ge layer part close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high-performance CMOS device including a Ge PMOS and a III-V NMOS by forming an MOS structure.

摘要翻译： 本发明提供具有共面锗（Ge）和III-V的杂化物的SOI半导体结构及其制备方法。 具有Ge和在绝缘体上共面的III-V族半导体材料的混合物的异质集成半导体结构包括形成在绝缘层上的至少一个Ge衬底，而另一衬底是形成在Ge上的III-V族半导体材料 半导体。 用于形成半导体结构的制备方法包括：制备全局Ge绝缘体衬底结构; 在Ge绝缘体衬底结构上制备III-V族III族半导体材料层; 第一次进行光刻和蚀刻，以形成图案化窗口到Ge层的上方以形成凹部; 在凹槽中制备间隔物; 通过选择性外延生长制备Ge膜; 进行化学机械抛光以获得具有Ge和III-V族半导体材料共面的混合物的异质集成半导体结构; 去除间隔物和靠近隔离物的缺陷Ge层部分; 实现Ge与III-V族III族半导体材料之间的隔离; 以及通过形成MOS结构来制备包括Ge PMOS和III-V NMOS的高性能CMOS器件。

公开(公告)号：US20130029478A1

公开(公告)日：2013-01-31

申请号：US13262656

申请日：2011-07-25

申请人： Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

发明人： Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

IPC分类号： H01L21/20

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation.

摘要翻译： 本发明公开了一种制造基于SOI衬底的高迁移率双通道材料的方法，其中压缩应变SiGe在常规SOI衬底上外延生长以用作PMOSFET的沟道材料; Si在SiGe上表面生长，采用离子注入和退火等方法，使部分应变SiGe弛豫并向其上的Si层转移应变，形成作为NMOSFET的沟道材料的应变Si材料。 通过简单的工艺和易于实现，该方法可以同时为NMOSFET和PMOSFET提供高迁移率沟道材料，可以很好地满足NMOSFET和PMOSFET器件同时提高性能的要求，从而为CMOS工艺提供潜在的沟道材料 下一代。

公开(公告)号：US08274119B2

公开(公告)日：2012-09-25

申请号：US12810648

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L21/70

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/78696

摘要： A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented.

摘要翻译： Ge和Si混合材料堆积模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由p型Ge和n型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在积累模式中，电流流过整个跑道状通道。 所公开的器件具有高的载流子迁移率，高的器件驱动电流，并且保持器件的电气完整性。 同时，防止了多晶硅栅极耗尽和短沟道效应。

公开(公告)号：US08274118B2

公开(公告)日：2012-09-25

申请号：US12810594

申请日：2010-02-11

申请人： DEYuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： DEYuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L21/70

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/12 ,  H01L29/42392 ,  H01L29/78696

摘要： A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.

摘要翻译： Ge和Si混合材料堆积模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有圆形截面并分别由p型Ge和n型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在累积模式下，电流流过整个圆柱形通道，以实现高载流子迁移率，降低低频噪声，防止多晶硅栅极耗尽和短沟道效应，并增加器件的阈值电压。