公开(公告)号：US07978118B1

公开(公告)日：2011-07-12

申请号：US12697789

申请日：2010-02-01

Applicant: Ahmed Abdell-Ra'oof Younis ,  Michael A. Nix

Inventor： Ahmed Abdell-Ra'oof Younis ,  Michael A. Nix

IPC: H03M1/34

CPC classification number: H03M1/0695 ,  H03M1/403

Abstract: A 1.5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage. The second voltage then is either increased or decreased by the reference voltage based on the polarity of the second voltage to generate the residual voltage used for the next conversion cycle in the series. Each bit pair is mapped to a corresponding two-bit code value and the resulting code values are used to generate the digital value.

Abstract translation: 1.5位算法模数转换器（ADC）产生代表输入电压的数字值。 ADC实现了转换操作的一系列转换周期。 每个转换周期具有三个子周期：缩放子周期，第一采样子周期和第二采样子周期。 在缩放子周期中，来自先前转换周期的剩余电压加倍以产生第一电压。 在第一采样子周期中，基于第一电压的极性来确定相应位对的第一位。 基于第一电压的极性，第一电压被增加或减小参考电压以产生第二电压。 在第二采样子周期中，基于第二电压的极性来确定相应位对的第二位。 然后，基于第二电压的极性，第二电压被增加或减小参考电压，以产生用于该系列中的下一个转换周期的剩余电压。 每个位对被映射到相应的两位代码值，并且所得到的代码值用于生成数字值。

公开(公告)号：US07852161B2

公开(公告)日：2010-12-14

申请号：US12353619

申请日：2009-01-14

Applicant: Michael A. Nix ,  Saeed Abbasi

Inventor： Michael A. Nix ,  Saeed Abbasi

IPC: H03B5/24

CPC classification number: H03K3/0315

Abstract: An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

Abstract translation: 振荡器。 所述振荡器包括具有第一多个反相器的第一环形振荡器，第一多个电容器，每个具有耦合到所述第一多个反相器中对应的一个反相器的输出端的第一端子，第二环形振荡器，具有第二多个反相器 以及第二多个电容器，每个电容器具有耦合到第二多个逆变器中对应的一个的输出端子的第一端子。 第一多个电容器的第二端子耦合到第二多个逆变器中对应的一个的输出端子。 第二多个电容器的第二端子耦合到第一多个逆变器中对应的一个的输出端子。 振荡器被配置为提供差分时钟信号作为输出。

公开(公告)号：US20100176889A1

公开(公告)日：2010-07-15

申请号：US12353619

申请日：2009-01-14

Applicant: Michael A. Nix ,  Saeed Abbasi

Inventor： Michael A. Nix ,  Saeed Abbasi

IPC: H03K3/03

CPC classification number: H03K3/0315

Abstract: An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

Abstract translation: 振荡器。 所述振荡器包括具有第一多个反相器的第一环形振荡器，第一多个电容器，每个具有耦合到所述第一多个反相器中对应的一个反相器的输出端的第一端子，第二环形振荡器，具有第二多个反相器 以及第二多个电容器，每个电容器具有耦合到第二多个逆变器中对应的一个的输出端子的第一端子。 第一多个电容器的第二端子耦合到第二多个逆变器中对应的一个的输出端子。 第二多个电容器的第二端子耦合到第一多个逆变器中对应的一个的输出端子。 振荡器被配置为提供差分时钟信号作为输出。

公开(公告)号：US07084683B1

公开(公告)日：2006-08-01

申请号：US10837185

申请日：2004-04-30

Applicant: Michael A. Nix

Inventor： Michael A. Nix

IPC: H03K3/283

CPC classification number: H03K3/356191 ,  H03K3/356113

Abstract: A differential flip-flop (400) has an output stage (402) with first and second input terminals (X1, X2), first and second output terminals (Q, Qb), a first voltage supply terminal (Vss), a first transistor (435) having a first current-handling terminal connected to the first output terminal (Q), a second current-handling terminal connected to the second output terminal (Qb), and a first control terminal connected to a clock signal (C). A second transistor has a third current-handling terminal connected to the first output terminal (Q), a fourth current-handling terminal connected to the voltage supply terminal (Vss), and a second control terminal connected to a first input terminal (X1) of the output stage. A third transistor (440) has a fifth current-handling terminal connected to the first output terminal (Q), a sixth current-handling terminal connected to the voltage supply terminal (Vss), and a third control terminal connected to the second output terminal (Qb).

Abstract translation: 差分触发器（400）具有带有第一和第二输入端（X 1，X 2），第一和第二输出端（Q，Qb），第一电压供应端（Vss）， 第一晶体管（435）具有连接到第一输出端子（Q）的第一电流处理端子，连接到第二输出端子（Qb）的第二电流处理端子和连接到时钟信号（C ）。 第二晶体管具有连接到第一输出端子（Q）的第三电流处理端子，连接到电压端子（Vss）的第四电流处理端子和连接到第一输入端子（X 1）的第二控制端子 ）的输出级。 第三晶体管（440）具有连接到第一输出端子（Q）的第五电流处理端子，连接到电压源端子（Vss）的第六电流处理端子，以及连接到第二输出端子 （Qb）。

公开(公告)号：US06677879B1

公开(公告)日：2004-01-13

申请号：US10224976

申请日：2002-08-20

Applicant: Michael A. Nix ,  Ahmed Younis

Inventor： Michael A. Nix ,  Ahmed Younis

IPC: H03M112

CPC classification number: H03M1/16 ,  H03M1/60

Abstract: A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.

Abstract translation: 输入模拟信号（105或405）的电压可以转换为频率取决于模拟输入信号（135或435）的信号。 分频器（115或415）可以被配置为将频率相关信号转换成分频信号（140或440）。 第一频率检测器（420a）或时间检测器（120a）可被配置为确定分频信号的频率，从而产生第一输出信号（145a或445a）。 第二频率检测器（420b）或时间检测器（120b）可以被配置为确定频率相关或非频率分频信号的频率，从而产生第二输出信号（145b或445b）。 第一和第二输出信号可以被后处理以产生代表输入模拟信号的数字输出信号（130或430）。

公开(公告)号：US5764581A

公开(公告)日：1998-06-09

申请号：US812931

申请日：1997-03-04

Applicant: Michael A. Nix

Inventor： Michael A. Nix

IPC: G11C11/404 ,  G11C11/4097 ,  G11C11/4099 ,  G11C11/419 ,  H03F3/45

CPC classification number: G11C11/4099 ,  G11C11/404 ,  G11C11/4097

Abstract: A dynamic RAM having two-transistor memory cells includes a top array of memory cells and a bottom array of memory cells, with a sense amplifier disposed between the two halves. The memory cells in each column of the top half are coupled to respective Bit.sub.-- Plus lines, and the memory cells in each column of the bottom half are coupled to respective Bit.sub.-- Minus lines. The Bit.sub.-- Plus lines and the Bit.sub.-- Minus lines are respectively coupled to Plus and Minus inputs of sense amplifiers for each column. One row of the top array includes only dummy cells, and one row of the bottom array includes only dummy cells. When a memory cell in the top array is read, a dummy cell in the lower array is activated, and when a memory cell in the bottom array is read, a dummy cell in the upper array is activated. That way, a two-transistor memory cell array can have a dual-differential bit line feature in order to reduce errors due to noise.

Abstract translation: 具有双晶体管存储单元的动态RAM包括存储单元的顶部阵列和存储单元的底部阵列，其中一个读出放大器设置在两个半部之间。 上半部分每列中的存储单元耦合到相应的Bit-Plus线，并且下半部分的每列中的存储器单元耦合到相应的Bit-Minus线。 Bit-Plus线和Bit-Minus线分别耦合到每列的读出放大器的Plus和Minus输入。 顶部阵列的一行仅包括虚拟单元，并且底部阵列的一行仅包括虚拟单元。 当读取顶部阵列中的存储单元时，下部阵列中的虚拟单元被激活，并且当读取底部阵列中的存储器单元时，上部阵列中的虚拟单元被激活。 这样，双晶体管存储单元阵列可以具有双差分位线特征，以便减少由噪声引起的误差。

公开(公告)号：US5272654A

公开(公告)日：1993-12-21

申请号：US766814

申请日：1991-09-26

Applicant: Michael A. Nix

Inventor： Michael A. Nix

IPC: G06F7/00 ,  G06F7/487 ,  G06F7/50 ,  G06F7/502 ,  G06F7/506 ,  G06F7/525 ,  G06F7/76 ,  H03M7/24 ,  G06F7/38

CPC classification number: G06F7/502 ,  H03M7/24

Abstract: A system for converting a floating point n-bit signed magnitude binary number to a fixed point two's complement binary number having m bits wherein m is greater than n, first converts the n bit signed magnitude binary number to a corresponding n-bit two's complement binary number. Thereafter, a shifter shifts the n-bit two's complement binary number to the left or right and by a number of bits responsive to received shift decode signals for providing the final fixed point m-bit two's complement binary number.

公开(公告)号：US4897810A

公开(公告)日：1990-01-30

申请号：US318098

申请日：1989-03-02

Applicant: Michael A. Nix

Inventor： Michael A. Nix

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: An asynchronous interrupt status bit circuit for use in conjunction with a microprocessor, which guarantees that no interrupting conditions are missed and that no single interrupting condition is indicated twice, includes a master latch (12), a transfer gate (14), a clocked latch (16), an inverter (18), an output driver circuit (20), and a clearing circuit (22, 24). The master latch (12) is responsive to an interrupt input signal for generating an interrupting logic signal at its output which is latched to a low logic level. The clearing circuit (22, 24) is responsive to a control signal for generating a clear signal to clear the output of the master latch (12) to a high level only when the control signal is latched at a high level before the time a true read signal is making a high-to-low transition. The next read signal causes an output signal having a low level to be read by the microprocessor if no interrupt input signal has occured.

Abstract translation: 与微处理器一起使用的异步中断状态位电路，其保证不会中断中断条件，并且没有单个中断条件被指示两次，包括主锁存器（12），传输门（14），时钟锁存器 （16），逆变器（18），输出驱动电路（20）和清零电路（22,24）。 主锁存器（12）响应于中断输入信号，用于在其输出端产生中断逻辑信号，锁存到低逻辑电平。 清除电路（22,24）响应于用于产生清除信号的控制信号，以便仅在控制信号在真实时间之前被锁存在高电平时才将主锁存器（12）的输出清除为高电平 读信号正在进行高到低的转换。 如果没有发生中断输入信号，则下一个读取信号使微处理器读取低电平的输出信号。

公开(公告)号：US08410833B2

公开(公告)日：2013-04-02

申请号：US13076071

申请日：2011-03-30

Applicant: Michael A. Nix ,  Golam R. Chowdhury ,  Curtis M. Brody ,  Faisal A. Syed

Inventor： Michael A. Nix ,  Golam R. Chowdhury ,  Curtis M. Brody ,  Faisal A. Syed

IPC: H03L7/00

CPC classification number: G06F1/24 ,  H03K17/223

Abstract: A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.

Abstract translation: 上电控制电路利用片上电路，多电压，环形振荡器和计数器以及边沿和电平检测电路来保证在上电条件下的复位，并用可变长度计数器继续复位状态，以保证可预测的复位 。 另外，在逻辑掉电状态之后提供干净的启动。

公开(公告)号：US07091773B1

公开(公告)日：2006-08-15

申请号：US10900945

申请日：2004-07-28

Applicant: Brian T. Brunn ,  Michael A. Nix

Inventor： Brian T. Brunn ,  Michael A. Nix

IPC: H03F1/36

CPC classification number: H03G11/02 ,  H03F1/34 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2203/45472 ,  H03F2203/45652 ,  H03G11/008

Abstract: A limiting circuit includes an input transconductance stage, an output transconductance stage, a feedback transconductance stage, first and second resistive loads, and a level limiting circuit. The input transconductance stage is operably coupled to convert an input voltage signal into an input current signal. The first resistive load is operably coupled to convert the input current signal and a feedback current signal into an intermediate output voltage signal. The output transconductance stage is operably coupled to convert the intermediate output voltage signal into an output current signal. The second resistive load is operably coupled to convert the output current signal into an output voltage signal. The feedback transconductance stage is operably coupled to produce the feedback current signal based on the output voltage signal. The level limiting module is operably coupled to limit at least one voltage level of the feedback transconductance stage.

Abstract translation: 限制电路包括输入跨导级，输出跨导级，反馈跨导级，第一和第二阻性负载以及电平限制电路。 输入跨导级可操作地耦合以将输入电压信号转换成输入电流信号。 第一电阻负载可操作地耦合以将输入电流信号和反馈电流信号转换成中间输出电压信号。 输出跨导级可操作地耦合以将中间输出电压信号转换成输出电流信号。 第二电阻负载可操作地耦合以将输出电流信号转换成输出电压信号。 反馈跨导级可操作地耦合以产生基于输出电压信号的反馈电流信号。 电平限制模块可操作地耦合以限制反馈跨导级的至少一个电压电平。