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20 条记录 (耗时 0.013 秒)

    Estimation of pin-to-pin timing for compiled blocks
    4.
    发明授权
    Estimation of pin-to-pin timing for compiled blocks 失效
    估计编译块的引脚到引脚时序

    公开(公告)号：US5596505A

    公开(公告)日：1997-01-21

    申请号：US96130

    申请日：1993-07-23

    申请人： Russell L. Steinweg ,  Michael A. Zampaglione ,  Pei H. Lin

    发明人： Russell L. Steinweg ,  Michael A. Zampaglione ,  Pei H. Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： A method for producing an electrical circuit by determining the input-to-output timing of compiled circuit blocks includes steps of determining a signal delay of a component due to physical characteristics of the component. The physical characteristics include at least a capacitance based upon relative placement of the component during compilation of a circuit block. The method further includes steps of determining an input-to-output speed for a circuit block by combining delays due to physical characteristics through alternate paths of the circuit block, and producing a compiled circuit block having a plurality of components by placing the components in the circuit block based on the steps of determining.

    摘要翻译： 通过确定编译的电路块的输入到输出定时来产生电路的方法包括由于该组件的物理特性确定组件的信号延迟的步骤。 物理特性至少包括基于组件在电路块编译期间的相对放置的电容。 该方法还包括以下步骤：通过组合通过电路块的交替路径的物理特性的延迟来确定电路块的输入到输出速度，以及通过将组件放置在所述电路块中来产生具有多个组件的编译电路块 电路块基于确定步骤。

    Automatic optimization of a compiled memory structure based on user selected criteria
    9.
    发明授权
    Automatic optimization of a compiled memory structure based on user selected criteria 失效
    根据用户选择的标准自动优化编译的内存结构

    公开(公告)号：US5625797A

    公开(公告)日：1997-04-29

    申请号：US148420

    申请日：1993-11-03

    申请人： Thomas V. Ferry ,  Russell L. Steinweg ,  Michael A. Zampaglione ,  Pei H. Lin

    发明人： Thomas V. Ferry ,  Russell L. Steinweg ,  Michael A. Zampaglione ,  Pei H. Lin

    IPC分类号： G11C7/10 ,  G06F12/02

    CPC分类号： G11C7/1006

    摘要： A block compiler system that allows a user to specify the total number of words and bits per word in a memory structure and to choose among alternative memory structures according to a user-selected criterion. In operation, the system varies the partitioning of memory address lines among column address lines and row address lines. Further, the system varies the internal memory structure according to a selected partitioning of memory address lines among column address lines and row address lines, and optimizes the memory structure based upon higher-level user-selected criteria.

    摘要翻译： 一种块编译器系统，其允许用户指定存储器结构中每个字的单词和位的总数，并根据用户选择的标准在备选存储器结构中进行选择。 在操作中，系统改变列地址线和行地址线之间的存储器地址线的划分。 此外，系统根据列地址线和行地址线之间的存储器地址线的选择分区来改变内部存储器结构，并且基于更高级别的用户选择的标准优化存储器结构。

    Method and apparatus for compensating for bit line delays in semiconductor memories
    10.
    发明授权
    Method and apparatus for compensating for bit line delays in semiconductor memories 失效
    用于补偿半导体存储器中的位线延迟的方法和装置

    公开(公告)号：US5245584A

    公开(公告)日：1993-09-14

    申请号：US632765

    申请日：1990-12-20

    申请人： Michael A. Zampaglione ,  Hai Van Phuong

    发明人： Michael A. Zampaglione ,  Hai Van Phuong

    IPC分类号： G11C7/14

    CPC分类号： G11C7/14

    摘要： A method for compensating for bit line delays in semiconductor memories including the steps of developing a dummy word line signal representative of the delay of a word line of a semiconductor memory and controlling the sense amplifier of the semiconductor memory with a control signal derived, at least in part, from the dummy word line signal. Preferably, the dummy word line signal is delayed by a fixed delay or by delay produced by a proportionally loaded dummy bit line. A circuit embodying the method of the present invention includes a dummy word which produces a dummy word signal upon the activation of any word of the semiconductor memory and a delay coupling the dummy word signal to the clock input of the sense amplifier. The delay may be a fixed delay including a number of logic elements, or it may be developed by a proportionally loaded bit line which has a fraction of the load of an actual bit line of the semiconductor memory. In either embodiment, the sense amplifier is clocked soon after the bit lines of the semiconductor memory are ready for sensing.

    摘要翻译： 一种用于补偿半导体存储器中的位线延迟的方法，包括以下步骤：开发代表半导体存储器的字线的延迟的虚拟字线信号，并且至少使用至少导出的控制信号来控制半导体存储器的读出放大器 部分地来自虚拟字线信号。 优选地，伪字线信号被延迟固定的延迟或由比例负载的虚拟位线产生的延迟。 体现本发明方法的电路包括在半导体存储器的任何字激活时产生虚拟字信号的虚拟字和将该哑字信号耦合到读出放大器的时钟输入的延迟。 延迟可以是包括多个逻辑元件的固定延迟，或者可以由具有半导体存储器的实际位线的负载的一部分的按比例加载的位线来开发。 在任一实施例中，在半导体存储器的位线准备好进行感测之后，读出放大器很快被计时。