公开(公告)号：US06670263B2

公开(公告)日：2003-12-30

申请号：US09802702

申请日：2001-03-10

申请人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

发明人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC分类号： H01L213205

CPC分类号： H01L21/28035 ,  H01L29/4925 ,  H01L29/665

摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

公开(公告)号：US06255200B1

公开(公告)日：2001-07-03

申请号：US09312943

申请日：1999-05-17

申请人： Arne W. Ballantine ,  Kevin K. Chan ,  Gary L. Langdeau ,  Michael B. Rice

发明人： Arne W. Ballantine ,  Kevin K. Chan ,  Gary L. Langdeau ,  Michael B. Rice

IPC分类号： H01L2136

CPC分类号： H01L21/28525 ,  C23C16/24 ,  Y10S148/122

摘要： A process for depositing polycrystalline silicon, including exposing a semiconductor substrate on which the polycrystalline silicon is to be deposited to a silicon containing gas and a temperature of about 680° C. to about 800° C.

摘要翻译： 一种用于沉积多晶硅的方法，包括将其上沉积多晶硅的半导体衬底暴露于含硅气体和约680℃至约800℃的温度。

公开(公告)号：US07094614B2

公开(公告)日：2006-08-22

申请号：US09681126

申请日：2001-01-16

申请人： Douglas S. Armbrust ,  John M. Baker ,  Arne W. Ballantine ,  Roger W. Cheek ,  Doreen D. DiMilia ,  Mark L. Reath ,  Michael B. Rice

发明人： Douglas S. Armbrust ,  John M. Baker ,  Arne W. Ballantine ,  Roger W. Cheek ,  Doreen D. DiMilia ,  Mark L. Reath ,  Michael B. Rice

IPC分类号： H01L21/66 ,  B05C11/00

CPC分类号： H01L21/28556 ,  C23C16/52

摘要： A method and apparatus are provided for controlling a CVD process used to deposit films on semiconductor substrates wherein the by-products of the reaction are measured and monitored during the reaction preferably using mass spectrometry and the results used to calculate the concentrations of the by-products and to control the CVD reaction process based on the by-product concentrations. An exemplary CVD process is the deposition of tungsten metal on a semiconductor wafer. A preferred method and apparatus uses a capillary gas sampling device for removing the by-product gases of the reaction as a feed for the mass spectrometer. The capillary gas sampling device is preferably connected to a differential pump.

公开(公告)号：US06893948B2

公开(公告)日：2005-05-17

申请号：US10616962

申请日：2003-07-11

申请人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

发明人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/20 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28035 ,  H01L29/4925 ,  H01L29/665

摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

摘要翻译： 通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。 所得到的结构可以具有两个或更多个相应晶粒尺寸的深度连续的区域，并且晶粒尺寸的选择被引导以最大限度地使栅极电介质附近的多晶硅中的掺杂剂活化最大化，并且将多晶硅的电阻定制在第一 区域并且远离栅极电介质。 该方法和所得结构有利地用于形成FET和掺杂多晶硅电阻器。

公开(公告)号：US06650000B2

公开(公告)日：2003-11-18

申请号：US09761123

申请日：2001-01-16

申请人： Arne W. Ballantine ,  Robert A. Groves ,  Jennifer L. Lund ,  James S. Nakos ,  Michael B. Rice ,  Anthony K. Stamper

发明人： Arne W. Ballantine ,  Robert A. Groves ,  Jennifer L. Lund ,  James S. Nakos ,  Michael B. Rice ,  Anthony K. Stamper

IPC分类号： H01L2900

CPC分类号： H01M10/052 ,  H01L23/522 ,  H01L23/58 ,  H01L2924/0002 ,  H01M4/5825 ,  H01M6/42 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/425 ,  H01L2924/00

摘要： A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices on a semiconductor wafer, followed by Back-End-Of-Line (BEOL) integration for wires connecting the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery is formed during BEOL integration within one or more wiring levels, and the conductive metallization conductively couples positive and negative terminals of the battery to the electronic devices. The battery may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.

摘要翻译： 在集成电路内提供电池的方法和结构，用于向存在于集成电路内的低电流电子器件提供电压。 该方法包括用于在半导体晶片上产生电子器件层的前端在线（FEOL）处理，随后是用于将电子器件连接在一起的线的后端（BEOL）集成，以形成完整的电 集成电路的电路。 BEOL集成包括在电子设备层上形成布线层的多层结构。 每个布线层包括嵌入在绝缘材料中的导电金属化（例如，金属镀通孔，导电布线等）。 电池在BEOL集成期间在一个或多个布线层次内形成，并且导电金属化将电池的正端子和负极端子电连接到电子设备。 相对于电池电极和电解质之间的结构和几何关系，电池可能具有几种不同的拓扑结构。 多个电池可以形成在一个或多个布线层中，并且可以导电地耦合到电子设备。 多个电池可以串联或并联连接。

公开(公告)号：US06489663B2

公开(公告)日：2002-12-03

申请号：US09753284

申请日：2001-01-02

申请人： Arne W. Ballantine ,  Robert A. Groves ,  Michael B. Rice ,  Anthony K. Stamper

发明人： Arne W. Ballantine ,  Robert A. Groves ,  Michael B. Rice ,  Anthony K. Stamper

IPC分类号： H01L2900

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated semiconducting device comprises a semiconducting substrate, a plurality of grounding strips disposed above the substrate in a lower metal level of the semiconducting device, an inductor positioned in an upper metal level of the semiconducting device, and a plurality of conducting vias connected to and extending away from the grounding strips towards the inductor. The inductor, conducting via, ground strips structure forms a Faraday cage that acts as a shield against electromagnetic radiation. The number and placement of the conductive vias are adjustable and can be optimized based on the relative importance of maximizing the quality factor Q of the inductor or minimizing the capacitance between the inductor and ground.

公开(公告)号：US07714366B2

公开(公告)日：2010-05-11

申请号：US10904565

申请日：2004-11-16

申请人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

发明人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L21/28035 ,  H01L29/4925 ,  H01L29/665

摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.

摘要翻译： 通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。 所得到的CMOS晶体管可以具有各自的晶粒尺寸的两个或更多个深度连续的区域，并且可以针对晶体尺寸的选择来最大化在栅极电介质附近的多晶硅中的掺杂剂活化，并且将多晶硅的电阻调整到高于该 第一区域并且远离栅极电介质。 多晶硅的区域可以具有作为从电介质膜的表面测量的距离的函数的变化的晶粒尺寸。

公开(公告)号：US07045372B2

公开(公告)日：2006-05-16

申请号：US10632652

申请日：2003-08-02

申请人： Arne W. Ballantine ,  Robert A. Groves ,  Jennifer L. Lund ,  James S. Nakos ,  Michael B. Rice ,  Anthony K. Stamper

发明人： Arne W. Ballantine ,  Robert A. Groves ,  Jennifer L. Lund ,  James S. Nakos ,  Michael B. Rice ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： H01M10/052 ,  H01L23/522 ,  H01L23/58 ,  H01L2924/0002 ,  H01M4/5825 ,  H01M6/42 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/425 ,  H01L2924/00

摘要： A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices on a semiconductor wafer, followed by Back-End-Of-Line (BEOL) integration for wires connecting the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery is formed during BEOL integration within one or more wiring levels, and the conductive metallization conductively couples positive and negative terminals of the battery to the electronic devices. The battery may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.