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    Strained-channel transistor device
    2.
    发明申请
    Strained-channel transistor device 有权
    应变通道晶体管器件

    公开(公告)号：US20080283877A1

    公开(公告)日：2008-11-20

    申请号：US12152353

    申请日：2008-05-13

    Applicant: Michael Collonge ,  Maud Vinet

    Inventor： Michael Collonge ,  Maud Vinet

    IPC: H01L29/84 ,  H01L21/00

    CPC classification number: H01L29/78654 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/78696

    Abstract: Semiconductor device comprising at least: one substrate, a transistor comprising at least one source region, one drain region, one channel and one gate, a planar layer based on at least one piezoelectric material, resting at least on the gate and capable of inducing at least mechanical strain on the transistor channel, in a direction that is substantially perpendicular to the plane of a face of the piezoelectric layer situated on the gate side, piezoelectric layer being arranged between two biasing electrodes, one of the two biasing electrodes being formed by a first layer based on at least one electrically conductive material such that the piezoelectric layer is arranged between this first conductive layer and the gate of the transistor.

    Abstract translation: 半导体器件至少包括：一个衬底，包括至少一个源极区，一个漏极区，一个沟道和一个栅极的晶体管，基于至少一个压电材料的平面层，至少搁在栅极上并能够诱导 在晶体管沟道上的基本上垂直于位于栅极侧的压电层的面的平面的方向上的最小机械应变，压电层布置在两个偏压电极之间，两个偏置电极之一由 基于至少一种导电材料的第一层，使得压电层布置在该第一导电层和晶体管的栅极之间。

    Strained-channel transistor device
    3.
    发明授权
    Strained-channel transistor device 有权
    应变通道晶体管器件

    公开(公告)号：US07973350B2

    公开(公告)日：2011-07-05

    申请号：US12152353

    申请日：2008-05-13

    Applicant: Michael Collonge ,  Maud Vinet

    Inventor： Michael Collonge ,  Maud Vinet

    IPC: H01L21/02

    CPC classification number: H01L29/78654 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/78696

    Abstract: Semiconductor device comprising at least: one substrate, a transistor comprising at least one source region, one drain region, one channel and one gate, a planar layer based on at least one piezoelectric material, resting at least on the gate and capable of inducing at least mechanical strain on the transistor channel, in a direction that is substantially perpendicular to the plane of a face of the piezoelectric layer situated on the gate side, the piezoelectric layer being arranged between two biasing electrodes, one of the two biasing electrodes being formed by a first layer based on at least one electrically conductive material such that the piezoelectric layer is arranged between this first conductive layer and the gate of the transistor.

    Abstract translation: 半导体器件至少包括：一个衬底，包括至少一个源极区，一个漏极区，一个沟道和一个栅极的晶体管，基于至少一个压电材料的平面层，至少搁在栅极上并能够诱导 晶体管沟道上的最小的机械应变在基本上垂直于位于栅极侧的压电层的面的平面的方向上，压电层设置在两个偏置电极之间，两个偏置电极之一由 基于至少一种导电材料的第一层，使得压电层布置在该第一导电层和晶体管的栅极之间。

    Suspended-gate MOS transistor with non-volatile operation
    4.
    发明授权
    Suspended-gate MOS transistor with non-volatile operation 有权
    具有非易失性操作的悬挂栅极MOS晶体管

    公开(公告)号：US07812410B2

    公开(公告)日：2010-10-12

    申请号：US12168417

    申请日：2008-07-07

    Applicant: Michael Collonge ,  Maud Vinet ,  Olivier Thomas

    Inventor： Michael Collonge ,  Maud Vinet ,  Olivier Thomas

    IPC: H01L27/20 ,  H01L41/04 ,  H01L41/083

    CPC classification number: G11C23/00 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/515 ,  H01L29/78654

    Abstract: A microelectronic device, including at least one transistor including: on a substrate, a semiconductor zone with a channel zone covered with a gate dielectric zone, a mobile gate, suspended above the gate dielectric zone and separated from the gate dielectric zone by an empty space, which the gate is located at an adjustable distance from the gate dielectric zone, and a piezoelectric actuation device including a stack formed by at least one layer of piezoelectric material resting on a first biasing electrode, and a second biasing electrode resting on the piezoelectric material layer, wherein the gate is attached to the first biasing electrode and is in contact with the first biasing electrode, and the piezoelectric actuation device is configured to move the gate with respect to the channel zone.

    Abstract translation: 一种微电子器件，包括至少一个晶体管，其包括：在衬底上，具有覆盖有栅极介电区的沟道区的半导体区，悬浮在栅极介电区上方的移动栅极，并与栅极介电区隔开空位 栅极位于与栅极介电区域可调节的距离处，以及压电致动装置，其包括由至少一层静电在第一偏置电极上的压电材料形成的叠层，以及沉积在压电材料上的第二偏置电极 层，其中所述栅极附接到所述第一偏置电极并且与所述第一偏置电极接触，并且所述压电致动装置被配置为相对于所述沟道区移动所述栅极。

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