Double slit-valve doors for plasma processing

    公开(公告)号:US07147719B2

    公开(公告)日:2006-12-12

    申请号:US10602491

    申请日:2003-06-23

    IPC分类号: H01L21/00 C23C16/00

    摘要: In a substrate vacuum processing chamber, a second inner slit passage door apparatus and method to supplement the normal slit valve and its door at the outside of the chamber. The inner slit passage door, blocks the slit passage at or adjacent the substrate processing location in a vacuum processing chamber to prevent process byproducts from depositing on the inner surfaces of the slit passage beyond the slit passage door and improves the uniformity of plasma in the processing chamber by eliminating a large cavity adjacent to the substrate processing location into which the plasma would otherwise expand. The inner slit passage door is configured and positioned in such a way as to avoid generating particles from the opening and closing motion of the second slit valve door, as it does not rub against any element of the chamber during its motion and the inner slit passage door is positioned with a predetermined gap from adjacent pieces and the door configuration includes beveled surfaces to further reduce the chance for particle generation, even when there is deposition of process byproducts on the door and its adjacent surfaces.

    Method and apparatus for etching photomasks

    公开(公告)号:US06534417B2

    公开(公告)日:2003-03-18

    申请号:US10126851

    申请日:2002-04-19

    IPC分类号: H01L2100

    摘要: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.

    Method and apparatus for etching photomasks
    3.
    发明授权
    Method and apparatus for etching photomasks 失效
    蚀刻光掩模的方法和设备

    公开(公告)号:US06391790B1

    公开(公告)日:2002-05-21

    申请号:US09625343

    申请日:2000-07-25

    IPC分类号: H01L2100

    摘要: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.

    摘要翻译: 提供了一种用于在诸如光掩模的基底中蚀刻硅基材料以形成具有直的侧壁,平坦的底部以及在侧壁和底部之间的高轮廓角度的特征并且使基底上的聚合物沉积物的形成最小化的方法。 在蚀刻工艺中,将基板定位在处理室中,将含氟碳氟化合物的处理气体(有利地是无氢氟碳化合物)引入处理室,其中基板保持在降低的温度,并且处理气体 在降低的功率水平下被激发成等离子体状态以蚀刻基板的硅基材料。 处理气体还可以包括惰性气体,例如氩气。

    Double slit-valve doors for plasma processing
    4.
    发明授权
    Double slit-valve doors for plasma processing 失效
    用于等离子体处理的双缝阀门

    公开(公告)号:US06192827B1

    公开(公告)日:2001-02-27

    申请号:US09111251

    申请日:1998-07-03

    IPC分类号: C23C1601

    摘要: In a substrate vacuum processing chamber, a second inner slit passage door apparatus and method to supplement the normal slit valve and its door at the outside of the chamber. The inner slit passage door, blocks the slit passage at or adjacent the substrate processing location in a vacuum processing chamber to prevent process byproducts from depositing on the inner surfaces of the slit passage beyond the slit passage door and improves the uniformity of plasma in the processing chamber by eliminating a large cavity adjacent to the substrate processing location into which the plasma would otherwise expand. The inner slit passage door is configured and positioned in such a way as to avoid generating particles from the opening and closing motion of the second slit valve door, as it does not rub against any element of the chamber during its motion and the inner slit passage door is positioned with a predetermined gap from adjacent pieces and the door configuration includes beveled surfaces to further reduce the chance for particle generation, even when there is deposition of process byproducts on the door and its adjacent surfaces.

    摘要翻译: 在基板真空处理室中,第二内狭缝通道门装置和方法,用于在室的外部补充普通狭缝阀及其门。 内部狭缝通道门在真空处理室中阻挡基板处理位置处或邻近的狭缝通道,以防止加工副产物沉积在狭缝通道的内表面上方超过狭缝通道门并改善处理中的等离子体的均匀性 通过消除与衬底处理位置相邻的大空腔,等离子体将在其中膨胀。 内狭缝通道门的构造和定位方式是避免从第二狭缝阀门的打开和关闭运动产生颗粒,因为它在其运动期间不会摩擦室内的任何元件,并且内部狭缝通道 门与相邻的件之间具有预定的间隙定位,并且门配置包括斜面以进一步减少颗粒产生的机会,即使在门及其相邻表面上沉积了工艺副产物。

    Adjusting DC bias voltage in plasma chambers
    5.
    发明授权
    Adjusting DC bias voltage in plasma chambers 失效
    调整等离子体室内的直流偏置电压

    公开(公告)号:US5891350A

    公开(公告)日:1999-04-06

    申请号:US666981

    申请日:1996-06-20

    摘要: A method of adjusting the cathode DC bias in a plasma chamber for fabricating semiconductor devices. A dielectric shield is positioned between the plasma and a selected portion of the electrically grounded components of the chamber, such as the electrically grounded chamber wall. The cathode DC bias is adjusted by controlling one or more of the following parameters: (1) the surface area of the chamber wall or other grounded components which is blocked by the dielectric shield; (2) the thickness of the dielectric; (3) the gap between the shield and the chamber wall; and (4) the dielectric constant of the dielectric material. In an apparatus aspect, the invention is a plasma chamber for fabricating semiconductor devices having an exhaust baffle with a number of sinuous passages. Each passage is sufficiently long and sinuous that no portion of the plasma within the chamber can extend beyond the outlet of the passage. By blocking the plasma from reaching the exhaust pump, the exhaust baffle reduces the deposition of unwanted particles on exhaust pump components. The exhaust baffle also reduces the cathode DC bias by reducing the effective surface area of the electrically grounded chamber wall which couples RF power to the plasma.

    摘要翻译: 一种调整用于制造半导体器件的等离子体室中的阴极直流偏压的方法。 电介质屏蔽件位于等离子体和室的电接地部件的选定部分之间,例如电接地室壁。 通过控制一个或多个以下参数来调节阴极直流偏压:(1)腔室壁的表面积或由介电屏蔽件阻挡的其它接地部件; (2)电介质的厚度; (3)屏蔽和室壁之间的间隙; 和(4)介电材料的介电常数。 在装置方面,本发明是用于制造半导体器件的等离子体室,其具有带有多个弯曲通道的排气挡板。 每个通道足够长和弯曲,使得室内的等离子体的任何部分不能延伸超过通道的出口。 通过阻止等离子体到达排气泵,排气挡板减少排气泵部件上不想要的颗粒的沉积。 排气挡板还通过减少将RF功率耦合到等离子体的电接地室壁的有效表面积来减小阴极DC偏压。

    Configurable single substrate wet-dry integrated cluster cleaner
    7.
    发明授权
    Configurable single substrate wet-dry integrated cluster cleaner 失效
    可配置单衬底湿干一体化清洁剂

    公开(公告)号:US06899111B2

    公开(公告)日:2005-05-31

    申请号:US09999751

    申请日:2001-10-31

    IPC分类号: B08B3/04 H01L21/00 B08B3/00

    摘要: The present invention provides a method and an apparatus for cleaning substrates. The cleaning chamber defines a processing cavity adapted to accommodate a substrate therein. In one embodiment, the cleaning chamber includes a chamber body having a processing cavity defined therein. A substrate is disposed in the processing cavity without contacting other chamber components by a Bernoulli effect and/or by a fluid cushion above and/or below the substrate. Fluid is flowed into the processing cavity at an angle relative to a radial line of the substrate to induce and/or control rotation of the substrate during a cleaning and drying process.

    摘要翻译: 本发明提供一种清洗基板的方法和装置。 清洁室限定适于在其中容纳衬底的处理腔。 在一个实施例中,清洁室包括具有限定在其中的处理空腔的室主体。 衬底被布置在处理空腔中,而不通过伯努利效应和/或衬底上方和/或下方的流体垫接触其它腔室部件。 流体相对于基底的径向线以一定角度流入处理空腔,以在清洁和干燥过程中引导和/或控制基底的旋转。

    Shield or ring surrounding semiconductor workpiece in plasma chamber
    8.
    发明授权
    Shield or ring surrounding semiconductor workpiece in plasma chamber 有权
    在等离子体室内围绕半导体工件的屏蔽或环

    公开(公告)号:US06689249B2

    公开(公告)日:2004-02-10

    申请号:US09947194

    申请日:2001-09-04

    IPC分类号: C23F108

    摘要: A ring or collar surrounding a semiconductor workpiece in a plasma chamber. According to one aspect, the ring has an elevated collar portion having an inner surface oriented at an obtuse angle to the plane of the workpiece, this angle preferably being 135°. This angular orientation causes ions bombarding the inner surface of the elevated collar to scatter in a direction more parallel to the plane of the workpiece, thereby reducing erosion of any dielectric shield at the perimeter of the workpiece, and ameliorating spatial non-uniformity in the plasma process due to any excess ion density near such perimeter. In a second aspect, the workpiece is surrounded by a dielectric shield, and the shield is covered by a non-dielectric ring which protects the dielectric shield from reaction with, or erosion by, the process gases. In a third aspect, the dielectric shield is thin enough to couple substantial power from the cathode to the plasma, thereby improving spatial uniformity of the plasma process near the perimeter of the workpiece. In a fourth aspect, azimuthal non-uniformities in process performance can be ameliorated by corresponding azimuthal variations in the dimensions of the elevated collar and/or the dielectric shield surrounding the workpiece.

    摘要翻译: 围绕等离子体室中的半导体工件的环或环。 根据一个方面,所述环具有提升的套环部分,其内表面以与工件的平面成钝角定向,该角度优选为135°。 这种角度取向导致离子轰击提升的套环的内表面沿更平行于工件的平面的方向散射,从而减少工件周边处的任何介电屏蔽的侵蚀,并且改善等离子体中的空间不均匀性 由于这种周边附近的任何过量的离子密度而产生的过程。 在第二方面,工件被电介质屏蔽围绕,屏蔽被非介电环覆盖,该绝缘环保护介电屏蔽免受过程气体的反应或腐蚀。 在第三方面中,电介质屏蔽体足够薄以将来自阴极的实质功率耦合到等离子体,从而改善靠近工件周边的等离子体工艺的空间均匀性。 在第四方面,方法性能的方位不均匀性可以通过围绕工件的高架轴环和/或介电屏蔽的尺寸的相应的方位角变化来改善。

    Apparatus for sidewall profile control during an etch process
    9.
    发明授权
    Apparatus for sidewall profile control during an etch process 失效
    在蚀刻过程中用于侧壁轮廓控制的装置

    公开(公告)号:US06248206B1

    公开(公告)日:2001-06-19

    申请号:US08724660

    申请日:1996-10-01

    IPC分类号: C23F102

    摘要: A process is provided for controlling the slope of the sidewalls of an opening produced in a semiconductor wafer during an etch process. Microwave or radio frequency energy is remotely applied to pre-excite a process gas. Radio frequency energy is also supplied to the process gas within the process chamber. The sidewall slope is varied by varying the ratio of the amount of remote microwave or radio frequency energy supplied and that of the radio frequency energy supplied within the process chamber. The sidewall slope is also shaped by controlling the process gas flow rate and composition, and the pressure within the process chamber. A more vertical, anisotropic etch profile is obtained with increased radio frequency energy and lower process chamber pressure. A more horizontal, isotropic profile is obtained with decreased radio frequency energy and higher process chamber pressure. A narrower etched feature having smaller interlayer and active element contact regions than the corresponding feature size on the overlying photoresist layer may thereby be provided.

    摘要翻译: 提供了一种用于控制在蚀刻工艺期间在半导体晶片中产生的开口的侧壁的斜率的工艺。 微波或射频能量被远程应用于预处理气体。 射频能量也被提供给处理室内的处理气体。 通过改变提供的远程微波或射频能量与处理室内提供的射频能量的比率来改变侧壁倾斜度。 侧壁倾斜也通过控制工艺气体流速和组成以及处理室内的压力来成形。 通过增加射频能量和较低的处理室压力获得更垂直的各向异性蚀刻轮廓。 通过降低射频能量和更高的处理室压力获得更水平,各向同性的曲线。 因此可以提供具有比覆盖的光致抗蚀剂层上的相应特征尺寸更小的中间层和有源元件接触区域的较窄蚀刻特征。

    Adjusting DC bias voltage in plasma chamber

    公开(公告)号:US06221782B1

    公开(公告)日:2001-04-24

    申请号:US09287701

    申请日:1999-04-06

    IPC分类号: H01L213065

    摘要: A method of adjusting the cathode DC bias in a plasma chamber for fabricating semiconductor devices. A dielectric shield is positioned between the plasma and a selected portion of the electrically grounded components of the chamber, such as the electrically grounded chamber wall. The cathode DC bias is adjusted by controlling one or more of the following parameters: (1) the surface area of the chamber wall or other grounded components which is blocked by the dielectric shield; (2) the thickness of the dielectric; (3) the gap between the shield and the chamber wall; and (4) the dielectric constant of the dielectric material. In an apparatus aspect, the invention is a plasma chamber for fabricating semiconductor devices having an exhaust baffle with a number of sinuous passages. Each passage is sufficiently long and sinuous that no portion of the plasma within the chamber can extend beyond the outlet of the passage. By blocking the plasma from reaching the exhaust pump, the exhaust baffle reduces the deposition of unwanted particles on exhaust pump components. The exhaust baffle also reduces the cathode DC bias by reducing the effective surface area of the electrically grounded chamber wall which couples RF power to the plasma.