公开(公告)号：US20120129311A1

公开(公告)日：2012-05-24

申请号：US13355221

申请日：2012-01-20

申请人： Rohit PAL ,  Frank Bin YANG ,  Michael J. HARGROVE

发明人： Rohit PAL ,  Frank Bin YANG ,  Michael J. HARGROVE

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

摘要： Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

摘要翻译： 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US07994014B2

公开(公告)日：2011-08-09

申请号：US12249570

申请日：2008-10-10

申请人： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

发明人： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02636 ,  H01L29/045 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

摘要： The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.

摘要翻译： 所公开的主题涉及半导体晶体管器件和相关的制造技术，其可以用于形成相对于常规硅化物触点具有增加的有效尺寸的硅化物触点。 根据本文公开的方法制造的半导体器件包括覆盖半导体材料层的半导体材料层和栅极结构。 沟道区形成在半导体材料层中，栅极结构下方的沟道区。 半导体器件还包括半导体材料层中的源区和漏区，其中沟道区位于源区和漏区之间。 此外，半导体器件包括覆盖源极和漏极区域的面形硅化物接触区域。

公开(公告)号：US07939852B2

公开(公告)日：2011-05-10

申请号：US12176835

申请日：2008-07-21

申请人： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

发明人： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC分类号： H01L31/0328

CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

摘要： Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

摘要翻译： 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US20110027978A1

公开(公告)日：2011-02-03

申请号：US12512814

申请日：2009-07-30

申请人： Michael J. HARGROVE ,  Frank Scott JOHNSON ,  Scott LUNING

发明人： Michael J. HARGROVE ,  Frank Scott JOHNSON ,  Scott LUNING

IPC分类号： H01L21/26 ,  H01L21/28

CPC分类号： H01L21/26586 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7847 ,  H01L29/785

摘要： Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.

摘要翻译： 提供了一种用于制造包括其上形成有多个凸起的晶体结构的基板的非平面半导体器件的方法的实施例。 在一个实施方案中，该方法包括以下步骤：将包含在多个凸起的晶体结构内的每个凸起的晶体结构的一部分非晶化，在多个凸起的晶体结构上形成牺牲应变层，以将应力施加到每个凸起晶体的非晶化部分 结构，退火所述非平面半导体器件以使应力存储状态下的每个凸起晶体结构的非晶化部分重结晶，以及去除所述牺牲应变层。

公开(公告)号：US20100308381A1

公开(公告)日：2010-12-09

申请号：US12480269

申请日：2009-06-08

申请人： Scott LUNING ,  Frank S. JOHNSON ,  Michael J. HARGROVE

发明人： Scott LUNING ,  Frank S. JOHNSON ,  Michael J. HARGROVE

IPC分类号： H01L29/78 ,  H01L21/22 ,  H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： Methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers and FinFET structures having such spacers are provided herein. In one embodiment, a method for fabricating a FinFET structure comprises fabricating a plurality of parallel fins overlying a semiconductor substrate. Each of the fins has sidewalls. A gate structure is fabricated overlying a portion of each of the fins. The gate structure has sidewalls and overlies channels within the fins. Stress-inducing sidewall spacers are formed about the sidewalls of the fins and the sidewalls of the gate structure. The stress-inducing sidewall spacers induce a stress within the channels. First conductivity-determining ions are implanted into the fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the fins.

摘要翻译： 本文提供了制造具有应力诱导源极/漏极形成间隔物的FinFET结构和具有这种间隔物的FinFET结构的方法。 在一个实施例中，制造FinFET结构的方法包括制造覆盖半导体衬底的多个平行散热片。 每个翅片都有侧壁。 制造覆盖每个翅片的一部分的栅极结构。 栅极结构在翅片内具有侧壁并覆盖通道。 应力诱导侧壁间隔件围绕翅片的侧壁和栅极结构的侧壁形成。 应力诱导侧壁间隔物在通道内引起应力。 使用应力诱导侧壁间隔物和栅极结构作为注入掩模将第一导电率确定离子注入到鳍中，以在翅片内形成源区和漏区。

公开(公告)号：US06613615B2

公开(公告)日：2003-09-02

申请号：US09976728

申请日：2001-10-12

申请人： Jack A. Mandelman ,  Fariborz Assaderaghi ,  Michael J. Hargrove ,  Peter Smeys ,  Norman J. Rohrer

发明人： Jack A. Mandelman ,  Fariborz Assaderaghi ,  Michael J. Hargrove ,  Peter Smeys ,  Norman J. Rohrer

IPC分类号： H01L2100

CPC分类号： H01L27/10897 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  Y10S257/901 ,  Y10S257/908

摘要： A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.

公开(公告)号：US06531741B1

公开(公告)日：2003-03-11

申请号：US09261333

申请日：1999-03-03

申请人： Michael J. Hargrove ,  Steven H. Voldman

发明人： Michael J. Hargrove ,  Steven H. Voldman

IPC分类号： H01L21265

CPC分类号： H01L29/66772 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/78603 ,  H01L29/78648

摘要： An SOI structure with a dual thickness buried insulating layer and method of forming the same is provided. A first substrate has raised portions each with a planar top surface. A dielectric layer covers the first substrate and its raised portions. The dielectric layer has a planar top surface. A second substrate layer is formed on the planar top surface of the dielectric layer. Semiconductor elements may be formed in the second substrate layer. The semiconductor elements pertain to core circuit elements, peripheral circuits, and electrostatic discharge (EDS) circuits.

摘要翻译： 提供具有双重厚度埋层绝缘层的SOI结构及其形成方法。 第一基板具有各自具有平坦的顶表面的凸起部分。 电介质层覆盖第一基板及其凸起部分。 电介质层具有平坦的顶表面。 在电介质层的平面顶表面上形成第二基底层。 半导体元件可以形成在第二基板层中。 半导体元件涉及核心电路元件，外围电路和静电放电（EDS）电路。

公开(公告)号：US06531375B1

公开(公告)日：2003-03-11

申请号：US09955375

申请日：2001-09-18

申请人： Kenneth J. Giewont ,  Eric Adler ,  Neena Garg ,  Michael J. Hargrove ,  Charles W. Koburger, III ,  Junedong Lee ,  Dominic J. Schepis ,  Isabel Ying Yang

发明人： Kenneth J. Giewont ,  Eric Adler ,  Neena Garg ,  Michael J. Hargrove ,  Charles W. Koburger, III ,  Junedong Lee ,  Dominic J. Schepis ,  Isabel Ying Yang

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76267

摘要： A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e.g. O2 implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a “touch-up” O2 implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the “touch-up” O2 implant (second ion implant), which in turn would result in a leaky BOX.

摘要翻译： 一种用于在SOI衬底上形成衬底接触区而不需要额外空间的新方法，并且为了提供较低的扩散电容。 该方法利用已知的半导体处理技术。 这种用于选择性地修改SOI衬底的BOX区域的方法包括首先提供硅衬底。 然后，使用SIMOX技术（例如，O 2注入）离子注入基底。 接下来，对基板进行光图案化以保护修改的BOX区域。 然后，使用“接触式”O2注入进一步进行离子注入，从而得到通常实施的良好质量BOX。 最后一步是退火基板。 存在掩模的衬底的区域将不会接收“接触”O 2注入（第二离子注入），这反过来将导致泄漏BOX。

公开(公告)号：US06372559B1

公开(公告)日：2002-04-16

申请号：US09709073

申请日：2000-11-09

申请人： Scott Crowder ,  Michael J. Hargrove ,  Suk Hoon Ku ,  L. Ronald Logan

发明人： Scott Crowder ,  Michael J. Hargrove ,  Suk Hoon Ku ,  L. Ronald Logan

IPC分类号： H01L2100

CPC分类号： H01L29/78696 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/78642 ,  H01L29/78648

摘要： A method of forming a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes processing steps that are CMOS compatible. The method include the steps of growing an oxide layer on a surface of a silicon-on-insulator (SOI) substrate, said SOI substrate having a buried oxide region located between a top Si-containing layer and a bottom Si-containing layer, wherein said top and bottom Si-containing layers are of the same conductivity-type; patterning and etching gate openings in said oxide layer, said top Si-containing layer and said buried oxide region stopping on said bottom Si-containing layer of said SOI substrate; forming a gate dielectric on exposed vertical sidewalls of said gate openings and filling said gate openings with silicon; removing oxide on horizontal surfaces which interface with said Si-containing bottom layer; recrystallizing silicon interfaced to said gate dielectric and filling said gate openings with expitaxial silicon; forming a mask on said oxide layer so as cover one of the silicon filled gate openings, while leaving an adjacent silicon filled gate opening exposed; selectively implanting dopants of said first conductivity-type into said exposed silicon filled gate opening and activating the same, wherein said dopants are implanted at an ion dosage of about 1E15 cm−2 or greater; selectively etching the exposed oxide layer and the underlying top Si-containing layer of said SOI substrate stopping on said buried oxide layer; removing said mask and implanting a graded-channel dopant profile in said previously covered silicon filled gate opening; etching any remaining oxide layer and forming spacers about said silicon filled gate openings; and saliciding any exposed silicon surfaces.

摘要翻译： 提供了一种形成自对准垂直双栅极金属氧化物半导体场效应晶体管（MOSFET）器件的方法，其包括与CMOS兼容的处理步骤。 该方法包括以下步骤：在绝缘体上硅（SOI）衬底的表面上生长氧化物层，所述SOI衬底具有位于顶部含Si层和底部含Si层之间的掩埋氧化物区域，其中 所述顶部和底部含Si层具有相同的导电型; 在所述氧化物层中图案化和蚀刻栅极开口，所述顶部含Si层和所述掩埋氧化物区停止在所述SOI衬底的所述底部含Si层上; 在所述栅极开口的暴露的垂直侧壁上形成栅极电介质，并用硅填充所述栅极开口; 在与所述含Si底层相接的水平表面上去除氧化物; 与所述栅介质接合的再结晶硅，并用外延硅填充所述栅极开口; 在所述氧化物层上形成掩模，以便覆盖硅填充的栅极开口中的一个，同时使相邻的硅填充的栅极开口暴露; 将所述第一导电类型的掺杂剂选择性地注入到所述暴露的硅填充的栅极开口中并使其激活，其中所述掺杂剂以约1E15cm-2或更大的离子剂量注入; 选择性地蚀刻暴露的氧化物层和停留在所述掩埋氧化物层上的所述SOI衬底的下层顶部含Si层; 去除所述掩模并在所述预先覆盖的硅填充的开口中注入分级沟道掺杂物分布; 蚀刻任何剩余的氧化物层并围绕所述硅填充的栅极开口形成间隔物; 并暴露任何硅表面。

公开(公告)号：US06369434B1

公开(公告)日：2002-04-09

申请号：US09363742

申请日：1999-07-30

申请人： Kai Chen ,  Scott W. Crowder ,  Liang-Kai Han ,  Michael J. Hargrove ,  Kam-Leung Lee ,  Hung Y. Ng

发明人： Kai Chen ,  Scott W. Crowder ,  Liang-Kai Han ,  Michael J. Hargrove ,  Kam-Leung Lee ,  Hung Y. Ng

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/36 ,  H01L29/7833

摘要： A p-type MOSFET having very shallow p-junction extensions. The semiconductor device is produced on a substrate by creating a layer of implanted nitrogen ions extending from the substrate surface to a predetermined depth preferably less than about 800 Å. The gate electrode serves as a mask so that the nitrogen implantation does not filly extend under the gate electrode. Boron is also implanted to an extent and depth comparable to the nitrogen implantation thereby forming very shallow p-junction extensions that remain confined substantially within the nitrogen layer even after thermal treatment. There is thus produced a pMOSFET having very shallow p-junction extensions in a containment layer of nitrogen and boron in the semiconductor material.

摘要翻译： 具有非常浅的p结延伸的p型MOSFET。 半导体器件通过产生从衬底表面延伸到预定深度优选小于约800的注入氮离子的层而在衬底上产生。 栅电极用作掩模，使得氮注入不会在栅极下方延伸。 硼也被植入到与氮注入相当的程度和深度，从而形成非常浅的p结延伸，即使在热处理之后仍保持约束在氮层内。 因此，在半导体材料中的氮和硼的容纳层中产生具有非常浅的p结延伸的pMOSFET。