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1.发明授权Method and apparatus for reducing bus bridge thrashing by temporarily masking agent requests to allow conflicting requests to be completed 失效通过临时屏蔽代理请求来减少总线桥跳转的方法和装置，以允许完成冲突的请求公开(公告)号：US06292865B1
公开(公告)日：2001-09-18
申请号：US09103622
申请日：1998-06-23
IPC分类号： G06F1338
CPC分类号： G06F13/364
摘要： A method and apparatus for masking processor requests to improve bus efficiency includes a bus bridge having a detection logic for determining when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value, with the first value being sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, is for masking requests from the first processor until the timer expires.
摘要翻译： 用于屏蔽处理器请求以提高总线效率的方法和装置包括具有用于确定第一总线上的第一处理器何时已经从第一总线退出预定次数的检测逻辑的总线桥。 当检测逻辑确定第一处理器已经从第一总线退出预定次数时，将定时器设置为第一值，其中第一值足以允许第二总线上的代理访问第一总线。 耦合到检测逻辑和定时器的屏蔽逻辑用于屏蔽来自第一处理器的请求，直到定时器期满。
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2.发明授权Method and apparatus for initializing a computer system having central and distributed address decode memory bus resources 失效用于初始化具有中央和分布式地址解码存储器总线资源的计算机系统的方法和装置
公开(公告)号：US5590289A
公开(公告)日：1996-12-31
申请号：US384472
申请日：1995-01-31
CPC分类号： G06F12/0653 , G06F12/0661 , G06F12/0684 , G06F9/445
摘要： A hybrid decoding module which resides on the computer system's high speed memory bus. The computer system incorporating the hybrid decoding module scheme is capable of having centrally decoded resources on the memory bus as well as resources capable of decoding memory bus addresses directly. During system initialization, or after a hard reset, the decoding logic polls each of the resources on the memory bus to determine whether the resource is a centrally decoded resource or a distributed decode resource. A table is maintained for all centrally decoded resources such that when addresses are put out by the processor during run-time, the decoding logic is capable of directing control to the centrally decoded resource. Another aspect of the present invention is implemented during the initialization of the system. When resources are polled by the decoding logic, they are also provided with an identifier which identifies the last available I/O space slot. If the memory bus resource requires this I/O space for its own use, it signals the decoding module that it should be assigned to that resource.
摘要翻译： 位于计算机系统的高速存储器总线上的混合解码模块。 结合混合解码模块方案的计算机系统能够在存储器总线上具有集中解码的资源以及能够直接解码存储器总线地址的资源。 在系统初始化期间或硬复位之后，解码逻辑轮询存储器总线上的每个资源以确定资源是集中解码的资源还是分布式解码资源。 维护所有中央解码的资源的表格，使得当运行时地址被处理器放出时，解码逻辑能够将控制权指向中央解码的资源。 在系统的初始化期间实现本发明的另一方面。 当资源被解码逻辑调查时，它们还被提供有识别最后可用的I / O空间时隙的标识符。 如果内存总线资源需要此I / O空间供其自己使用，则会向解码模块发出应该分配给该资源的信号。
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公开(公告)号：US07190715B1
公开(公告)日：2007-03-13
申请号：US09471435
申请日：1999-12-23
IPC分类号： H04B1/38
CPC分类号： H04M11/062
摘要： An asymmetric digital subscriber loop modem may achieve efficiency and cost reduction by providing a coder/decoder (codec) chip which transmits data externally of the chip when the data is at a reduced or lower data rate. That is, instead of transmitting the data at a higher data rate, which may result in increased cost, for example for EMI shielding, the codec chip transmits the data when the data is at a reduced data rate.
摘要翻译： 非对称数字用户环路调制解调器可以通过提供一种编码器/解码器（编解码器）芯片来实现效率和成本降低，当编码器/解码器（编解码器）芯片在数据处于降低或较低数据速率时，该芯片在芯 也就是说，代替以更高的数据速率发送可能导致成本增加的数据，例如对于EMI屏蔽，当数据处于降低的数据速率时，编解码芯片发送数据。
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公开(公告)号：US06594717B2
公开(公告)日：2003-07-15
申请号：US10237113
申请日：2002-09-09
IPC分类号： G06F1300
CPC分类号： G06F13/385
摘要： Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.
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5.发明授权Method and apparatus for reducing bus bridge thrashing by temporarily masking agent requests to allow conflicting requests to be completed 失效通过临时屏蔽代理请求来减少总线桥跳转的方法和装置，以允许完成冲突的请求
公开(公告)号：US5850557A
公开(公告)日：1998-12-15
申请号：US644833
申请日：1996-05-10
IPC分类号： G06F13/364 , G06F13/38
CPC分类号： G06F13/364
摘要： A method and apparatus for masking processor requests to improve bus efficiency includes a bus bridge having a detection logic for determining when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value, with the first value being sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, is for masking requests from the first processor until the timer expires.
摘要翻译： 用于屏蔽处理器请求以提高总线效率的方法和装置包括具有用于确定第一总线上的第一处理器何时已经从第一总线退出预定次数的检测逻辑的总线桥。 当检测逻辑确定第一处理器已经从第一总线退出预定次数时，将定时器设置为第一值，其中第一值足以允许第二总线上的代理访问第一总线。 耦合到检测逻辑和定时器的屏蔽逻辑用于屏蔽来自第一处理器的请求，直到定时器期满。
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公开(公告)号：US07028209B2
公开(公告)日：2006-04-11
申请号：US10436837
申请日：2003-05-13
CPC分类号： G06F13/4045 , H04L5/18
摘要： A bus repeater with voltage conversion and multiplexing circuits for use between devices with incompatible voltage levels communicating over inter-integrated circuit (I2C) buses. Bi-directional data and clock lines are passed through the circuit from one bus to the other, blocked so they are not passed on, or modified before being passed on, depending on the current transaction. The repeater is placed between two separate I2C buses and communicates between the two buses. To accommodate the slow-slave requirements of an I2C bus, the duration of signals on the clock line may be modified.
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公开(公告)号：US06549967B1
公开(公告)日：2003-04-15
申请号：US09439046
申请日：1999-11-12
申请人： Michael J. McTague
发明人： Michael J. McTague
IPC分类号： G06F1300
CPC分类号： G06F13/423
摘要： A PCI bus system for a computer provides a main board with one or more PCI slots mounted on the board, and with each PCI slot adapted to receive a PCI card. Each PCI slot includes a plurality of electrical contacts. A multiplexor is provided for each PCI slot, and each multiplexor has at least first and second sets of electrical inputs selectively connectable to a set of outputs connected to a first set of the electrical contacts on its respective PCI slot. A link controller is provided for each PCI slot, with each link controller mounted on the main board. A first plurality of electrical lines for each PCI slot connect the respective link controller to the first set of electrical inputs on the respective multiplexor. A PCI controller is mounted on the main board, with a second-plurality of electrical lines connecting the PCI controller to the second set of electrical inputs on the multiplexor. Also provided are a third plurality of electrical lines connecting the PCI controller to each of a second set of electrical contacts on each PCI slot, wherein the contacts of the second set are different from the first set.
摘要翻译： 用于计算机的PCI总线系统为主板提供安装在板上的一个或多个PCI插槽，并且每个PCI插槽适于接收PCI卡。 每个PCI插槽包括多个电触点。 为每个PCI插槽提供多路复用器，并且每个多路复用器具有至少第一组和第二组电输入，可选择性地连接到连接到其相应PCI插槽上的第一组电触头组的一组输出。 为每个PCI插槽提供链路控制器，每个链路控制器安装在主板上。 用于每个PCI插槽的第一组多条电线将相应的链路控制器连接到相应复用器上的第一组电输入。 PCI控制器安装在主板上，第二多条电线将PCI控制器连接到多路复用器上的第二组电输入。 还提供了将PCI控制器连接到每个PCI插槽上的第二组电触点中的每一个上的第三组多条电线，其中第二组的触点与第一组不同。
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公开(公告)号：US06678776B2
公开(公告)日：2004-01-13
申请号：US10402012
申请日：2003-03-28
申请人： Michael J. McTague
发明人： Michael J. McTague
IPC分类号： G06F1300
CPC分类号： G06F13/423
摘要： A PCI bus system for a computer provides a main board with one or more PCI slots mounted on the board, and with each PCI slot adapted to receive a PHI card. Each PCI slot includes a plurality of electrical contacts. A multiplexor is provided for each PCI slot, and each multiplexor has at least first and second sets of electrical inputs selectively connectable to a set of outputs connected to a first set of the electrical contacts on its respective PCI slot. A link controller is provided for each PCI slot, with each link controller mounted on the main board. A first plurality of electrical lines for each PCI slot connect the respective link controller to the first set of electrical inputs on the respective multiplexor. A PCI controller is mounted on the main board, with a second plurality of electrical lines connecting the PHI controller to the second set of electrical inputs on the multiplexor. Also provided are a third plurality of electrical lines connecting the PCI controller to each of a second set of electrical contacts on each PCI slot, wherein the contacts of the second set are different from the first set.
摘要翻译： 用于计算机的PCI总线系统为主板提供安装在板上的一个或多个PCI插槽，并且每个PCI插槽适于接收PHI卡。 每个PCI插槽包括多个电触点。 为每个PCI插槽提供多路复用器，并且每个多路复用器具有至少第一组和第二组电输入，可选择性地连接到连接到其相应PCI插槽上的第一组电触头组的一组输出。 为每个PCI插槽提供链路控制器，每个链路控制器安装在主板上。 用于每个PCI插槽的第一组多条电线将相应的链路控制器连接到相应复用器上的第一组电输入。 PCI控制器安装在主板上，第二组多条电线将PHI控制器连接到多路复用器上的第二组电气输入。 还提供了将PCI控制器连接到每个PCI插槽上的第二组电触点中的每一个上的第三组多条电线，其中第二组的触点与第一组不同。
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公开(公告)号：US06597197B1
公开(公告)日：2003-07-22
申请号：US09385495
申请日：1999-08-27
IPC分类号： H03K190175
CPC分类号： G06F13/4045 , H04L5/18
摘要： A bus repeater with voltage conversion and multiplexing circuits for use between devices with incompatible voltage levels communicating over inter-integrated circuit (I2C) buses. Bi-directional data and clock lines are passed through the circuit from one bus to the other, blocked so they are not passed on, or modified before being passed on, depending on the current transaction. The repeater is placed between two separate I2C buses and communicates between the two buses. Separating the two buses in this manner permits each bus to operate at a different voltage. Multiplexing is achieved by including logic in the repeater to recognize a first address associated with the repeater received from the first bus, and pass subsequent addresses and their associated messages through to the second bus to be decoded and processed by the devices on that bus. When the first address is not associated with the repeater, subsequent addresses and their associated messages are ignored and not passed through. To accommodate the slow-slave requirements of an I2C bus, the duration of signals on the clock line may be modified.
摘要翻译： 具有电压转换和多路复用电路的总线中继器，用于通过内部集成电路（I2C）总线通信的不兼容电压电平的器件之间使用。 双向数据和时钟线路通过电路从一个总线传递到另一个总线，阻止它们在传递之前不会传递或修改，这取决于当前事务。 中继器放置在两条独立的I2C总线之间，并在两条总线之间进行通信。 以这种方式分离两条总线允许每个总线以不同的电压工作。 通过在中继器中包括逻辑来识别与从第一总线接收的中继器相关联的第一地址，并将后续地址及其相关联的消息传递到第二总线以由该总线上的设备解码和处理来实现多路复用。 当第一个地址不与中继器相关联时，后续地址及其关联的消息将被忽略，不会被传递。 为了适应I2C总线的慢速从机要求，可能会修改时钟线上的信号持续时间。
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10.发明授权Apparatus and method for dedicated interconnection over a shared external bus 失效通过共享外部总线进行专用互连的装置和方法公开(公告)号：US06502146B1
公开(公告)日：2002-12-31
申请号：US09537087
申请日：2000-03-29
IPC分类号： G06F1300
CPC分类号： G06F13/385
摘要： Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.
摘要翻译： 控制外部总线的装置和方法。 在一个实施例中，装置包括外部总线端口和外部总线控制器。 外部总线控制器可以包括用于接收第一组数据的第一寄存器接口和用于接收第二组数据的第二寄存器接口。 外部总线控制器可以将第一组数据和第二组数据发送到所述外部总线端口。
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