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    Interlocked increment memory allocation and access
    1.
    发明授权
    Interlocked increment memory allocation and access 有权
    联锁增量内存分配和访问

    公开(公告)号：US09529632B2

    公开(公告)日：2016-12-27

    申请号：US12553652

    申请日：2009-09-03

    Applicant: Michael Mantor ,  John McCardle ,  Marcos Zini ,  Brian Emberling

    Inventor： Michael Mantor ,  John McCardle ,  Marcos Zini ,  Brian Emberling

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/50

    CPC classification number: G06F9/5016

    Abstract: A method of allocating a memory to a plurality of concurrent threads is presented. The method includes dynamically determining writer threads each having at least one pending write to the memory; and dynamically allocating respective contiguous blocks in the memory for each of the writer threads. Another method of allocating a memory to a plurality of concurrent threads includes launching the plurality of threads as a plurality of wavefronts, dynamically determining a group of wavefronts each having at least one thread requiring a write to the memory, and dynamically allocating respective contiguous blocks in the memory for each wavefront from the group of wavefronts. A corresponding method of assigning a memory to a plurality of reader threads includes determining a first number corresponding to a number of writer threads having a block allocated in said memory, launching a first number of reader threads, entering a first wavefront of said reader threads from said group of wavefronts to an atomic operation, and assigning a first block in the memory to the first wavefront during the corresponding atomic operation, where the first block is contiguous to a previously allocated block dynamically allocated to another wavefront from said group of wavefronts. Corresponding system embodiments and computer program product embodiments are also presented.

    Abstract translation: 提出了一种向多个并发线程分配存储器的方法。 该方法包括动态地确定写入器线程，每个写入器线程具有至少一个待写入到存储器的 并为每个写入器线程动态地分配存储器中的相应连续块。 向多个并发线程分配存储器的另一种方法包括：将多个线程作为多个波前发射，动态地确定每组具有至少一个需要对存储器进行写入的线程的波前组，以及动态分配相应的连续块 从波浪组的每个波前的记忆。 将存储器分配给多个读取器线程的相应方法包括确定与具有在所述存储器中分配的块的写入器线程数相对应的第一数字，启动第一数量的读取器线程，从所述读取器线程的第一波前输入 所述波束组合到原子操作，并且在相应的原子操作期间将第一块在存储器中分配给第一波阵面，其中第一块与先前分配的块相邻，所述块先前从所述波阵组中分配给另一波阵面。 还提出了相应的系统实施例和计算机程序产品实施例。

    Multithreaded Computing
    3.
    发明申请
    Multithreaded Computing 审中-公开
    多线程计算

    公开(公告)号：US20130191852A1

    公开(公告)日：2013-07-25

    申请号：US13606741

    申请日：2012-09-07

    Applicant: Lee W. Howes ,  Benedict R. Gaster ,  Michael Clair Houston ,  Michael Mantor

    Inventor： Lee W. Howes ,  Benedict R. Gaster ,  Michael Clair Houston ,  Michael Mantor

    IPC: G06F9/46

    CPC classification number: G06F9/542 ,  G06F9/4843

    Abstract: A system, method, and computer program product are provided for improving resource utilization of multithreaded applications. Rather than requiring threads to block while waiting for data from a channel or requiring context switching to minimize blocking, the techniques disclosed herein provide an event-driven approach to launch kernels only when needed to perform operations on channel data, and then terminate in order to free resources. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.

    Abstract translation: 提供了一种系统，方法和计算机程序产品，用于提高多线程应用程序的资源利用率。 而不是要求线程在等待来自信道的数据或需要上下文切换以最小化阻塞的情况下阻塞，所以本文所公开的技术提供了仅当需要对信道数据执行操作时启动内核的事件驱动方法，然后终止以便 免费资源。 这些操作在硬件中有效地处理，但是具有足够的灵活性，可以在各种编程模型中实现。

    Apparatus with redundant circuitry and method therefor
    7.
    发明授权
    Apparatus with redundant circuitry and method therefor 有权
    具有冗余电路的装置及其方法

    公开(公告)号：US08281183B2

    公开(公告)日：2012-10-02

    申请号：US12509803

    申请日：2009-07-27

    Applicant: Michael Mantor ,  Ralph Clayton Taylor ,  Robert Scott Hartog

    Inventor： Michael Mantor ,  Ralph Clayton Taylor ,  Robert Scott Hartog

    IPC: G06F11/00

    CPC classification number: G06F11/2028 ,  G06F11/2038 ,  G06F11/2048

    Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

    Abstract translation: 具有电路冗余的装置包括一组并行算术逻辑单元（ALU），冗余并行ALU，输入数据移位逻辑，其耦合到该组并行ALU并且可操作地耦合到冗余并行ALU。 输入数据移位逻辑将有缺陷的ALU的输入数据沿第一方向移动到该组中的相邻ALU。 当相邻的ALU是组中的最后一个或结束ALU时，移位逻辑继续将没有故障的结束ALU的输入数据移动到冗余并行ALU。 冗余的并行ALU然后对有缺陷的ALU进行操作。 输出数据移位逻辑耦合到并行冗余ALU和所有其他ALU输出的输出，以使输出数据在与输入移位逻辑相反的方向上相反的方向上移位，以重新输出用于继续处理的数据输出，包括用于存储或用于 由其他电路进一步处理。

    Interlocked Increment Memory Allocation and Access
    8.
    发明申请
    Interlocked Increment Memory Allocation and Access 有权
    联锁增量内存分配和访问

    公开(公告)号：US20110055511A1

    公开(公告)日：2011-03-03

    申请号：US12553652

    申请日：2009-09-03

    Applicant: Michael MANTOR ,  John MCCARDLE ,  Marcos ZINI ,  Brian EMBERLING

    Inventor： Michael MANTOR ,  John MCCARDLE ,  Marcos ZINI ,  Brian EMBERLING

    IPC: G06F12/02 ,  G06F12/00 ,  G06F9/46

    CPC classification number: G06F9/5016

    Abstract: A method of allocating a memory to a plurality of concurrent threads is presented. The method includes dynamically determining writer threads each having at least one pending write to the memory; and dynamically allocating respective contiguous blocks in the memory for each of the writer threads. Another method of allocating a memory to a plurality of concurrent threads includes launching the plurality of threads as a plurality of wavefronts, dynamically determining a group of wavefronts each having at least one thread requiring a write to the memory, and dynamically allocating respective contiguous blocks in the memory for each wavefront from the group of wavefronts. A corresponding method of assigning a memory to a plurality of reader threads includes determining a first number corresponding to a number of writer threads having a block allocated in said memory, launching a first number of reader threads, entering a first wavefront of said reader threads from said group of wavefronts to an atomic operation, and assigning a first block in the memory to the first wavefront during the corresponding atomic operation, where the first block is contiguous to a previously allocated block dynamically allocated to another wavefront from said group of wavefronts. Corresponding system embodiments and computer program product embodiments are also presented.

    Abstract translation: 提出了一种向多个并发线程分配存储器的方法。 该方法包括动态地确定写入器线程，每个写入器线程具有至少一个待写入到存储器的 并为每个写入器线程动态地分配存储器中的相应连续块。 向多个并发线程分配存储器的另一种方法包括：将多个线程作为多个波前发射，动态地确定每组具有至少一个需要对存储器进行写入的线程的波前组，以及动态分配相应的连续块 从波浪组的每个波前的记忆。 将存储器分配给多个读取器线程的相应方法包括确定与具有在所述存储器中分配的块的写入器线程数相对应的第一数字，启动第一数量的读取器线程，从所述读取器线程的第一波前输入 所述波束组合到原子操作，并且在相应的原子操作期间将第一块在存储器中分配给第一波阵面，其中第一块与先前分配的块相邻，所述块先前从所述波阵组中分配给另一波阵面。 还提出了相应的系统实施例和计算机程序产品实施例。

    Processing Unit with a Plurality of Shader Engines
    9.
    发明申请
    Processing Unit with a Plurality of Shader Engines 有权
    具有多个着色引擎的处理单元

    公开(公告)号：US20110050716A1

    公开(公告)日：2011-03-03

    申请号：US12691541

    申请日：2010-01-21

    Applicant: Michael MANTOR ,  Ralph C. Taylor ,  Jeffrey T. Brady

    Inventor： Michael MANTOR ,  Ralph C. Taylor ,  Jeffrey T. Brady

    IPC: G09G5/00

    CPC classification number: G06T15/005

    Abstract: A processor includes a first shader engine and a second shader engine. The first shader engine is configured to process pixel shaders for a first subset of pixels to be displayed on a display device. The second shader engine is configured to process pixel shaders for a second subset of pixels to be displayed on the display device. Both the first and second shader engines are also configured to process general-compute shaders and non-pixel graphics shaders. The processor may also include a level-one (L1) data cache, coupled to and positioned between the first and second shader engines.

    Abstract translation: 处理器包括第一着色引擎和第二着色引擎。 第一个着色引擎被配置为处理要在显示设备上显示的第一子像素的像素着色器。 第二着色引擎被配置为处理要显示在显示设备上的第二像素子像素的像素着色器。 第一和第二着色引擎都配置为处理通用计算着色器和非像素图形着色器。 处理器还可以包括耦合到第一和第二着色引擎之间并定位在第一和第二着色引擎之间的一级（L1）数据高速缓存。

    GRAPHICS PROCESSING LOGIC WITH VARIABLE ARITHMETIC LOGIC UNIT CONTROL AND METHOD THEREFOR
    10.
    发明申请
    GRAPHICS PROCESSING LOGIC WITH VARIABLE ARITHMETIC LOGIC UNIT CONTROL AND METHOD THEREFOR 有权
    具有可变算术逻辑单元控制的图形处理逻辑及其方法

    公开(公告)号：US20060053189A1

    公开(公告)日：2006-03-09

    申请号：US11161674

    申请日：2005-08-11

    Applicant: Michael Mantor

    Inventor： Michael Mantor

    IPC: G06F7/38

    CPC classification number: G06T15/005 ,  G06F11/2028 ,  G06F11/2038 ,  G06F11/2048

    Abstract: Briefly, graphics data processing logic includes a plurality of parallel arithmetic logic units (ALUs), such as floating point processors or any other suitable logic, that operate as a vector processor on at least one of pixel data and vertex data (or both) and a programmable storage element that contains data representing which of the plurality of arithmetic logic units are not to receive data for processing. The graphics data processing logic also includes parallel ALU data packing logic that is operatively coupled to the plurality of arithmetic logic processing units and to the programmable storage element to pack data only for the plurality of arithmetic logic units identified by the data in the programmable storage element as being enabled.

    Abstract translation: 简而言之，图形数据处理逻辑包括多个并行算术逻辑单元（ALU），诸如浮点处理器或任何其它合适的逻辑，其在像素数据和顶点数据（或两者）中的至少一个上作为向量处理器，以及 可编程存储元件，其包含表示多个算术逻辑单元中的哪一个不接收用于处理的数据的数据。 图形数据处理逻辑还包括并行ALU数据打包逻辑，其可操作地耦合到多个算术逻辑处理单元和可编程存储元件，以仅对由可编程存储元件中的数据标识的多个算术逻辑单元打包数据 被启用。

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