公开(公告)号：US4055802A

公开(公告)日：1977-10-25

申请号：US713910

申请日：1976-08-12

申请人： Peter Theodore Panousis ,  Robert Leonard Pritchett ,  Friedolf Michael Smits

发明人： Peter Theodore Panousis ,  Robert Leonard Pritchett ,  Friedolf Michael Smits

IPC分类号： G11C17/00 ,  G06F11/00 ,  G06F11/26 ,  G11C5/00 ,  G11C17/08 ,  H01L21/822 ,  H01L21/8229 ,  H01L27/02 ,  H01L27/04 ,  H01L27/102 ,  G01R15/12 ,  G01R31/30

CPC分类号： G06F11/006 ,  G06F11/26 ,  G11C17/08 ,  G11C5/00 ,  H01L27/02

摘要： For identification purposes, a network is added to a multiply configurable microminiature array. During fabrication of the array, the connection pattern of the network is established to be uniquely representative of the particular circuit then being formed in the array. In response to interrogation signals applied to the array, the network provides a unique pattern of voltages representative of the particular circuit. During actual operation of the array, the identification network is in effect automatically disconnected therefrom.

摘要翻译： 为了识别目的，将网络添加到多重可配置的微型阵列中。 在阵列的制造期间，建立网络的连接模式以唯一地代表然后形成在阵列中的特定电路。 响应于施加到阵列的询问信号，网络提供代表特定电路的独特的电压模式。 在阵列的实际操作期间，识别网络实际上与其自动断开连接。

公开(公告)号：US20060273056A1

公开(公告)日：2006-12-07

申请号：US11433828

申请日：2006-05-15

申请人： Michael Smits ,  Lance Perrin

发明人： Michael Smits ,  Lance Perrin

IPC分类号： A47B47/00

CPC分类号： A47F5/01

摘要： The display rack of the present invention includes a main frame, at least two shelf receiving portions, a plurality of shelves and at least one basket, peg hook basket or reel assembly. The main frame has a back portion and side portions. Each shelf receiving portion is attached to the main frame and has a plurality of generally vertically spaced apart shelf receiving apertures formed therein. Each shelf has spaced apart shelf fingers adapted to be received in the shelf receiving apertures. The plurality of shelves is chosen from the group consisting of shelf basket racks and shelf reel racks. In another aspect of the invention there is provided a web basket for use in association with hanging products. The web basket includes a hook portion, a basket portion and a means for attaching the basket to a shelf. The basket portion is spaced below the hook portion.

摘要翻译： 本发明的显示架包括主框架，至少两个搁架接收部分，多个架子和至少一个篮子，钉钩篮或卷轴组件。 主框架具有后部和侧部。 每个搁架接收部分附接到主框架并且具有形成在其中的多个大致垂直间隔的搁架接收孔。 每个搁板具有适于容纳在搁板接收孔中的间隔开的搁板指状物。 多个货架选自货架架架和货架卷架。 在本发明的另一方面，提供了一种用于与悬挂产品相关联的网篮。 网篮包括钩部，篮部和用于将篮附接到搁架的装置。 筐部分在钩部下方间隔开。

公开(公告)号：US20080036007A1

公开(公告)日：2008-02-14

申请号：US11875217

申请日：2007-10-19

申请人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

发明人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

公开(公告)号：US20070007548A1

公开(公告)日：2007-01-11

申请号：US11160705

申请日：2005-07-06

申请人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

发明人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

IPC分类号： H01L21/8234 ,  H01L27/10 ,  H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

公开(公告)号：US20080045039A1

公开(公告)日：2008-02-21

申请号：US11873721

申请日：2007-10-17

申请人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

发明人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

IPC分类号： H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.