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7 条记录 (耗时 0.014 秒)

    Logic circuit for use in D/A converter having ECL-type gate structure
    4.
    发明授权
    Logic circuit for use in D/A converter having ECL-type gate structure 失效
    用于具有ECL型栅极结构的D / A转换器的逻辑电路

    公开(公告)号：US5034630A

    公开(公告)日：1991-07-23

    申请号：US476539

    申请日：1990-02-07

    申请人： Hisashi Sugiyama ,  Michinori Nakamura ,  Yasuhiro Sugimoto

    发明人： Hisashi Sugiyama ,  Michinori Nakamura ,  Yasuhiro Sugimoto

    IPC分类号： H03K19/086 ,  H03M7/00 ,  H03M7/14 ,  H03M7/16

    CPC分类号： H03M7/14 ,  H03K19/0866 ,  H03M7/165

    摘要： A logic circuit outputs state signals of seven different kinds, on the basis of first, second and third digital signals. A first composite gate circuit outputs a logical OR among the first to third digital signals as a first state signal. A first gate circuit outputs a logical OR between the second and third digital signals as a second state signal. A second composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical OR between the supplied logical AND and the third digital signal as third state signal. A third composite gate circuit is supplied with a logical OR between the first and second digital signals, and outputs a logical AND between the supplied logical OR and the third digital signal as a fifth state signal. A second gate circuit outputs a logical AND between the second and third digital signals as a sixth state signal. A fourth composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical AND between the supplied logical AND and the third digital signal as a seventh state signal. The third digital signal is output as a fourth state signal without being processed. Each of the above circuits has an emitter coupled logic structure.

    Bi-CMOS logic gate circuits for low-voltage semiconductor integrated circuits
    5.
    发明授权
    Bi-CMOS logic gate circuits for low-voltage semiconductor integrated circuits 失效
    用于低电压半导体集成电路的BI-CMOS逻辑门电路

    公开(公告)号：US5146118A

    公开(公告)日：1992-09-08

    申请号：US649901

    申请日：1991-02-01

    申请人： Michinori Nakamura ,  Yasuhiro Sugimoto

    发明人： Michinori Nakamura ,  Yasuhiro Sugimoto

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H03K19/013 ,  H03K19/0944

    CPC分类号： H03K19/0136 ,  H03K19/09448

    摘要： A Bi-CMOS logic gate circuit according to the present invention comprises a complementary Bi-CMOS output circuit at the output stage composed of a first-polarity bipolar transistor and a second-polarity bipolar transistor, and a level compensation circuit, provided between the input and output terminals of the Bi-CMOS output circuit, which compensates for each forward-bias voltage between the base and emitter of the first-polarity and second-polarity bipolar transistors. This arrangement allows the Bi-CMOS output circuit to swing the output voltage from the voltage of the high-voltage supply to that of the low-voltage supply at the output stage, previously smaller in the amplitude by the amount equal to the sum of the base-emitter voltage of two bipolar transistors.

    Voltage level converting circuit
    6.
    发明授权
    Voltage level converting circuit 失效
    电压电平转换电路

    公开(公告)号：US4695750A

    公开(公告)日：1987-09-22

    申请号：US770090

    申请日：1985-08-28

    申请人： Hiroyuki Hara ,  Michinori Nakamura ,  Yasuhiro Sugimoto

    发明人： Hiroyuki Hara ,  Michinori Nakamura ,  Yasuhiro Sugimoto

    IPC分类号： H03K19/017 ,  H03K19/0175 ,  H03K19/092 ,  H03K17/10 ,  H03K19/003 ,  H03K19/086

    CPC分类号： H03K19/017527 ,  H03K19/01707

    摘要： A voltage level converting circuit includes first and second potential terminals between which a power source voltage is applied, first and second terminals for receiving an input signal and an inverted input signal, a differential amplifier including npn transistors whose conduction states are controlled by the input signal and the inverted input signal, and an output circuit for generating an output logic signal corresponding to the output voltage of the differential amplifier. The output circuit of this voltage level converting circuit has a current path connected in series between the first and second potential terminals by way of a constant current source, and includes a MOS transistor whose conduction state is controlled by the output voltage of the differential amplifier.

    摘要翻译： 电压电平转换电路包括施加电源电压的第一和第二电位端子，用于接收输入信号的第一和第二端子和反相输入信号，包括npn晶体管的差分放大器，其导通状态由输入信号 和反相输入信号，以及用于产生与差分放大器的输出电压对应的输出逻辑信号的输出电路。 该电压电平转换电路的输出电路具有通过恒流源串联连接在第一和第二电位端子之间的电流路径，并且包括MOS晶体管，其导通状态由差分放大器的输出电压控制。

    Interface circuit preventing noise generated between integrated circuits
    7.
    发明授权
    Interface circuit preventing noise generated between integrated circuits 失效
    接口电路防止集成电路之间产生的噪声

    公开(公告)号：US5072139A

    公开(公告)日：1991-12-10

    申请号：US343203

    申请日：1989-04-26

    申请人： Michinori Nakamura

    发明人： Michinori Nakamura

    IPC分类号： H03K5/08 ,  H03K19/0175 ,  H03K19/018

    CPC分类号： H03K19/01806

    摘要： An interface circuit includes a power source terminal, an input terminal and NPN transistor. Th interface circuit further includes a first resistor connected between the emitter of the NPN transistor and the input terminal, a second resistor connected between the collector of the NPN transistor and the power source terminal, a diode connected in a forward direction between the collector of the NPN transistor and the power source terminal and a voltage dividing circuit for biasing the base of the NPN transistor to a preset potential.