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1.发明公开公开(公告)号：US20240365538A1
公开(公告)日：2024-10-31
申请号：US18765605
申请日：2024-07-08
IPC分类号： H10B12/00 , G11C11/402 , H01L23/49 , H01L23/538 , H01L29/66 , H01L29/78
CPC分类号： H10B12/488 , G11C11/4023 , H01L23/49 , H01L23/538 , H01L29/66666 , H01L29/7827 , H10B12/053 , H10B12/30 , H10B12/31 , H10B12/315 , H10B12/34
摘要： Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.
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公开(公告)号：US20240361949A1
公开(公告)日：2024-10-31
申请号：US18652604
申请日：2024-05-01
发明人： Yanhua Bi
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F12/0246 , G06F12/0253 , G06F2212/7205
摘要： Methods, systems, and devices for host initiated garbage collection are described. In some examples, a user accessible application or public interface of a host system may initiate a garbage collection procedure for a memory system using one or more vendor commands. For example, the host system and the memory system may support a first vendor command to check a fragmentation status or fragmentation parameter of the of the memory system. Additionally, the host system and the memory system may support a second vendor command to initiate a garbage collection procedure at the memory system, or to interrupt an ongoing garbage collection procedure. The host system and the memory system may also support a third vendor command to check the status of an initiated garbage collection procedure.
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3.发明授权公开(公告)号：US12132155B2
公开(公告)日：2024-10-29
申请号：US17145752
申请日：2021-01-11
IPC分类号： H01L33/52 , H01L21/56 , H01L21/683 , H01L21/78 , H01L23/00 , H01L23/31 , H01L33/00 , H01L33/20 , H01L33/44 , H01L33/62 , H01S5/02 , H10K50/84 , H10K50/844 , H10K71/00
CPC分类号： H01L33/52 , H01L21/561 , H01L21/78 , H01L23/3185 , H01L33/0095 , H01L33/20 , H01L33/44 , H01L33/62 , H01S5/0201 , H01L21/6836 , H01L24/11 , H01L24/13 , H01L24/97 , H01L2221/68327 , H01L2221/68377 , H01L2224/1146 , H01L2224/13022 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/97 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2933/005 , H01L2933/0066 , H10K50/84 , H10K50/844 , H10K71/00 , H10K71/851 , Y02P80/30 , H01L2224/97 , H01L2224/11 , H01L2224/1146 , H01L2924/00014 , H01L2224/13124 , H01L2924/00014 , H01L2224/13147 , H01L2924/00014 , H01L2224/13144 , H01L2924/00014 , H01L2224/13139 , H01L2924/00014 , H01L2924/12041 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2924/12044 , H01L2924/00
摘要： Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation in accordance with one embodiment includes forming a plurality of trenches by etching through a metallic bond material forming a bond between a carrier substrate and a plurality of the dies and singulating the carrier substrate along the trenches to separate the dies. In particular embodiments, the trenches extend into the carrier substrate. In further particular embodiments, the dies are at least partially encapsulated in a dielectric material.
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公开(公告)号：US12131768B2
公开(公告)日：2024-10-29
申请号：US17896337
申请日：2022-08-26
发明人： Kang-Yong Kim , Yang Lu
IPC分类号： G11C11/406 , G11C11/4078 , G11C11/408
CPC分类号： G11C11/40618 , G11C11/40615 , G11C11/4078 , G11C11/4085
摘要： Systems and methods for multi-wordline direct refresh operations in response to a row hammer error in a memory bank. The approach includes detecting, by a row hammer mitigation component, a row hammer error in a memory bank; and then triggering, by the row hammer mitigation component, a response to the row hammer error. Further, a memory controller receives, from a mode register, data, based on an aliasing row counter policy, selecting a type of multi-wordline direct refresh operation to be performed on a plurality of victim memory rows within the memory bank, wherein the plurality of victim memory rows are dispersed across a plurality of memory sub-banks. The approach includes concurrently executing the selected multi-wordline direct refresh operation to the plurality of victim memory rows.
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公开(公告)号：US12131073B2
公开(公告)日：2024-10-29
申请号：US18522726
申请日：2023-11-29
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0613 , G06F3/0635 , G06F3/0679
摘要： A set of submission queues associated with a host system is identified. A first set of internal queues and a second set of internal queues is generated based on the set of submission queues. Responsive to fetching a first memory access command pending in a submission queue of the set of submission queues, a first internal queue of the first set of internal queues is populated. Responsive to processing the first memory access command from the first internal queue of the first set of internal queues, a second internal queue of the second set of internal queues is populated. Responsive to completion of the first memory access command from the second internal queue of the second set of internal queues, an indication of the completion of the first memory access command is returned to the host system.
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公开(公告)号：US12131041B2
公开(公告)日：2024-10-29
申请号：US17680183
申请日：2022-02-24
发明人： Luca Bert
IPC分类号： G06F3/06
CPC分类号： G06F3/0632 , G06F3/0604 , G06F3/0659 , G06F3/0683
摘要： A system includes one or more memory devices and a processing device coupled to the memory device(s) to perform operations including receiving a first set of data items from a host system to be programmed to the one or more memory devices. The operations include determining, in view of a first zone group identifier associated with the first set of data items, that each data item of the first set of data items is to be programed to one or more zones associated with a first zone group identified by the first zone group identifier. The operations include identifying a first set of zones across the one or more memory devices that match a size associated with the first zone group and that satisfy a programming parallelism criterion. The operations include programming each of the first set of data items to memory cells residing at the identified first set of zones.
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公开(公告)号：US12130748B2
公开(公告)日：2024-10-29
申请号：US18225958
申请日：2023-07-25
发明人： Sanjay Subbarao
IPC分类号： G06F12/10 , G06F12/0875 , G06F12/1009
CPC分类号： G06F12/1009 , G06F12/0875 , G06F2212/608
摘要： A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.
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公开(公告)号：US12130747B2
公开(公告)日：2024-10-29
申请号：US18081468
申请日：2022-12-14
发明人： Sharath Chandra Ambula , David Aaron Palmer , Venkata Kiran Kumar Matturi , Sri Ramya Pinisetty , Sushil Kumar
IPC分类号： G06F12/1009
CPC分类号： G06F12/1009 , G06F2212/657
摘要： Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.
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公开(公告)号：US20240357809A1
公开(公告)日：2024-10-24
申请号：US18637129
申请日：2024-04-16
发明人： Zeyar Lin Aung , Kaiming Luo , Saurabh Jagdishbhai Kasodariya , Sumeet C. Pandey , Brittany L. Kohoutek , Yuwei Ma , Kyle A. Ritter
IPC分类号： H10B43/20
CPC分类号： H10B43/20
摘要： Methods, systems, and devices for support structures for tier deflection in a memory system are described. The memory system may include a word line contact that extends through a stack of materials and lands on a tier of a word line. The word line contact may be between four support structures that form a diamond around the word line contact. Two support structures that form opposite vertices of the diamond may align centrally with the word line contact in a lateral direction and two other support structures that form opposite vertices of the diamond may align centrally with the word line contact in a longitudinal direction.
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10.发明公开公开(公告)号：US20240357793A1
公开(公告)日：2024-10-24
申请号：US18619425
申请日：2024-03-28
IPC分类号： H10B12/00
CPC分类号： H10B12/00
摘要： A microelectronic device comprises a first transistor structure, a second transistor structure vertically overlying the first transistor structure, a storage device vertically overlying the second transistor structure, a first conductive contact structure contacting the first transistor structure, the second transistor structure, and a first electrode of the storage device, and a second conductive contact structure configured to be in electrical communication with the first transistor structure and the second transistor structure. Related memory devices and electronic systems are also described.
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