公开(公告)号：US06410440B1

公开(公告)日：2002-06-25

申请号：US09305977

申请日：1999-05-05

Applicant: Charles F. Drill ,  Milind Weling

Inventor： Charles F. Drill ,  Milind Weling

IPC: H01L21302

CPC classification number: H01L21/3212 ,  B24B37/042 ,  H01L21/31053

Abstract: A method of using a gaseous environment providing improved control of CMP process. In one embodiment, the method comprises several steps. One step involves placing a semiconductor wafer onto a polishing pad of a CMP machine. A subsequent step dispenses a slurry onto the polishing pad. Another step provides a blanket of gas that displaces the ambient atmosphere surrounding the semiconductor wafer. In another step, the blanket of gas is maintained around the semiconductor wafer during the CMP operation.

Abstract translation: 一种使用气体环境提供改进的CMP工艺控制的方法。 在一个实施例中，该方法包括几个步骤。 一步涉及将半导体晶片放置在CMP机器的抛光垫上。 随后的步骤将浆料分配到抛光垫上。 另一个步骤提供了一个气体覆盖物，其覆盖半导体晶片周围的环境大气。 在另一步骤中，在CMP操作期间，气体保护层保持在半导体晶片周围。

公开(公告)号：US06353261B1

公开(公告)日：2002-03-05

申请号：US09303891

申请日：1999-05-03

Applicant: Milind Weling

Inventor： Milind Weling

IPC: H01L2348

CPC classification number: H01L23/522 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus for reducing interconnect resistance using optimized trench geometry. One embodiment comprises an interconnect line and an interconnect well. The interconnect line, comprised of a conductive material, has a depth and exists in a first circuit layer of a multilayered Integrated Circuit (IC). The interconnect well is coupled to the interconnect line and is insulated from other conductive materials in the first circuit layer, and in the plurality of subsequent adjacent layers. The interconnect well has a depth in said multilayered IC that exceeds said depth of said interconnect line.

Abstract translation: 一种使用优化沟槽几何形状降低互连电阻的设备。 一个实施例包括互连线和互连阱。 由导电材料构成的互连线具有深度并存在于多层集成电路（IC）的第一电路层中。 互连阱耦合到互连线，并且与第一电路层中的其它导电材料以及多个随后的相邻层绝缘。 互连阱在所述多层IC中具有超过所述互连线的所述深度的深度。

公开(公告)号：US5399533A

公开(公告)日：1995-03-21

申请号：US161642

申请日：1993-12-01

Applicant: Dipankar Pramanik ,  Vivek Jain ,  Milind Weling

Inventor： Dipankar Pramanik ,  Vivek Jain ,  Milind Weling

IPC: H01L21/768 ,  H01R ,  H01R4/64

CPC classification number: H01L21/76819

Abstract: An integrated circuit fabrication method begins with semiconductor devices formed on a substrate. A patterned metal layer is deposited on the substrate to connect the semiconductor devices. A nitride layer is deposited over the metal layer and substrate. The nitride layer topography comprises hills located over metal regions and valleys located over non-metal regions. Spin-on-glass (SOG) is deposited over the nitride layer, thereby filling the valleys and covering the hills. The SOG layer and the nitride layer hills are etched back at substantially the same etch rate, using plasma etching, to form a planar surface. An oxide layer is then deposited over the planar surface to encapsulate the semiconductor devices, metal layer, nitride layer and SOG layer. Vias may then be etched through the oxide layer and the nitride layer to expose portions of the underlying metal layer and facilitate upper layer metal connections thereto. A second metal layer is deposited on the oxide layer and the fabrication process continues until the integrated circuit is complete.

Abstract translation: 集成电路制造方法从形成在衬底上的半导体器件开始。 图案化的金属层沉积在衬底上以连接半导体器件。 氮化物层沉积在金属层和衬底上。 氮化物层形貌包括位于非金属区域上的金属区域和山谷之上的山丘。 旋转玻璃（SOG）沉积在氮化物层上，从而填充谷并覆盖山丘。 使用等离子体蚀刻以基本相同的蚀刻速率回蚀SOG层和氮化物层丘，以形成平坦表面。 然后在平面表面上沉积氧化物层以封装半导体器件，金属层，氮化物层和SOG层。 然后可以将通孔蚀刻通过氧化物层和氮化物层以暴露下面的金属层的部分，并促进与其的上层金属连接。 第二金属层沉积在氧化物层上，制造过程继续进行，直到集成电路完成。

公开(公告)号：US06319796B1

公开(公告)日：2001-11-20

申请号：US09377043

申请日：1999-08-18

Applicant: Olivier Laparra ,  Ramiro Solis ,  Hunter Brugge ,  Michela S. Love ,  Bijan Moslehi ,  Milind Weling

Inventor： Olivier Laparra ,  Ramiro Solis ,  Hunter Brugge ,  Michela S. Love ,  Bijan Moslehi ,  Milind Weling

IPC: H01L2176

CPC classification number: H01L21/76224 ,  Y10S148/05

Abstract: Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate regions that are to be electrically isolated from one another. A dielectric material is deposited in the trenches by exposure to a high density plasma having a first deposition-to-etch ratio. The high density plasma is adjusted to a second deposition-to-etch ratio greater than the first ratio to accumulate the dielectric material on the substrate after at least partially filling the trenches. A portion of the dielectric material is removed to planarize the workpiece. A number of components, such as insulated gate field effect transistors, may be subsequently formed in the substrate regions between the trenches.

Abstract translation: 公开了提供集成电路的技术，包括提供改进的集成电路隔离结构。 这些技术包括在集成电路衬底中形成多个沟槽以限定要彼此电绝缘的多个衬底区域。 通过暴露于具有第一沉积到蚀刻比的高密度等离子体，在沟槽中沉积电介质材料。 将高密度等离子体调整到大于第一比率的第二沉积蚀刻比，以在至少部分地填充沟槽之后在基板上积累电介质材料。 去除介电材料的一部分以使工件平坦化。 可以随后在沟槽之间的衬底区域中形成多个组件，例如绝缘栅场效应晶体管。

公开(公告)号：US06193860B1

公开(公告)日：2001-02-27

申请号：US09298629

申请日：1999-04-23

Applicant: Milind Weling

Inventor： Milind Weling

IPC: C25B904

CPC classification number: C25D17/12 ,  C25D7/12 ,  C25D17/001 ,  C25D21/12

Abstract: An apparatus for optimizing electrical currents to improve copper plating uniformity on a semiconductor wafer is disclosed. The use of multiple anodes of the embodiment provides for variable electrical currents to the semiconductor wafer, the variable feature of the variable electrical currents compensating for non-uniform electroplating characteristics.

Abstract translation: 公开了一种用于优化电流以提高半导体晶片上的镀铜均匀性的装置。 本实施例的多个阳极的使用提供了对半导体晶片的可变电流，可变电流的可变特征补偿了不均匀的电镀特性。

公开(公告)号：US6022265A

公开(公告)日：2000-02-08

申请号：US100276

申请日：1998-06-19

Applicant: Charles F. Drill ,  Calvin Gabriel ,  Milind Weling ,  Richard Russ ,  David E. Henderson

Inventor： Charles F. Drill ,  Calvin Gabriel ,  Milind Weling ,  Richard Russ ,  David E. Henderson

IPC: B24B53/007 ,  B24B53/013 ,  B24B53/017 ,  B24B1/00

CPC classification number: B24B53/017 ,  B24B53/013

Abstract: A complementary conditioning system for use in chemical mechanical polishing (CMP). The present invention functions with a CMP machine adapted for polishing a semiconductor wafer having tungsten components fabricated thereon. A polishing pad is mounted on the CMP machine. The polishing pad has a polishing surface configured for polishing the semiconductor wafer and its tungsten components. The performance of the polishing surface is characterized by a polishing efficiency. A complementary end-effector is mounted on the CMP machine. The complementary end-effector is adapted to chemically complement the tungsten components on the semiconductor wafer. The complementary end-effector is further adapted to contact the polishing surface and improve the polishing efficiency by chemically enhancing the polishing surface, thereby obtaining a more efficient removal rate for the chemical mechanical polishing.

Abstract translation: 用于化学机械抛光（CMP）的补充调理系统。 本发明与适用于抛光其上制造有钨成分的半导体晶片的CMP机器相结合。 抛光垫安装在CMP机器上。 抛光垫具有被配置用于抛光半导体晶片及其钨组分的抛光表面。 研磨表面的性能的特征在于抛光效率。 互补的末端执行器安装在CMP机器上。 互补末端执行器适于化学补充半导体晶片上的钨成分。 补充的末端执行器还适于接触抛光表面并且通过化学增强抛光表面来提高抛光效率，从而获得用于化学机械抛光的更有效的去除速率。

公开(公告)号：US08679981B1

公开(公告)日：2014-03-25

申请号：US12943808

申请日：2010-11-10

Applicant: Milind Weling ,  Judy Huckabay ,  Abdurrahman Sezginer

Inventor： Milind Weling ,  Judy Huckabay ,  Abdurrahman Sezginer

IPC: H01L21/302

CPC classification number: H01L21/033 ,  G03F1/00

Abstract: Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

Abstract translation: 本发明的各种实施例提供用于半导体器件制造和生成用于图案化线特征和大特征的目标布局的光掩模的系统和方法。 本发明的实施例涉及使用自对准双重图案来定义线特征和大特征的目标布局的系统和方法。

公开(公告)号：US20090146322A1

公开(公告)日：2009-06-11

申请号：US11952703

申请日：2007-12-07

Applicant: MILIND WELING ,  Abdurrahman Sezginer

Inventor： MILIND WELING ,  Abdurrahman Sezginer

IPC: H01L23/48 ,  H01L21/311 ,  G06F17/50

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

Abstract: Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques. According to another embodiment, features for lines and logic device components having a width greater than that of the lines are formed in the spacer material in the same mask layer.

Abstract translation: 公开了半导体器件制造方法。 示例性方法包括在半导体衬底上沉积第一图案的过程，其中第一图案限定宽而窄的空间; 在衬底上的第一图案上沉积间隔物材料; 蚀刻间隔物材料，使得间隔物材料从基底和第一图案的水平表面移除，但保持邻近由第一图案限定的宽空间的垂直表面，并保持在由第一图案限定的狭窄空间内; 并从衬底去除第一图案。 在一个实施例中，第一图案可以包括牺牲材料，其可以包括例如多晶硅材料。 沉积可以包括物理气相沉积，化学气相沉积，电化学沉积，分子束外延，原子层沉积或其它沉积技术。 根据另一个实施例，在相同掩模层中的间隔物材料中形成具有大于线的宽度的线和逻辑器件部件的特征。

公开(公告)号：US07018282B1

公开(公告)日：2006-03-28

申请号：US08824633

申请日：1997-03-27

Applicant: Charles Franklin Drill ,  Milind Weling

Inventor： Charles Franklin Drill ,  Milind Weling

IPC: B24D11/00

CPC classification number: B24B37/20 ,  B24B37/042 ,  B24B37/26

Abstract: The present invention comprises a customized polishing pad for use in a wafer polishing machine. The polishing pad of the present invention includes a polishing surface integral with the polishing pad. The polishing surface is adapted to frictionally contact a wafer in the polishing machine, thereby polishing the wafer. The polishing surface of the polishing pad includes at least two areas, where each area is adapted to frictionally contact the wafer and achieve a polishing effect specific for that area. A customized polishing effect is achieved by the polishing pad of the present invention when the wafer is selectively moved frictionally against the at least two areas by the wafer polishing machine.

公开(公告)号：US06572439B1

公开(公告)日：2003-06-03

申请号：US09572564

申请日：2000-05-16

Applicant: Charles Franklin Drill ,  Milind Weling

Inventor： Charles Franklin Drill ,  Milind Weling

IPC: B24B4900

CPC classification number: B24B37/20 ,  B24B37/042 ,  B24B37/26

Abstract: The present invention comprises a customized polishing pad for use in a wafer polishing machine. The polishing pad of the present invention includes a polishing surface integral with the polishing pad. The polishing surface is adapted to frictionally contact a wafer in the polishing machine, thereby polishing the wafer. The polishing surface of the polishing pad includes at least two areas, where each area is adapted to frictionally contact the wafer and achieve a polishing effect specific for that area. A customized polishing effect is achieved by the polishing pad of the present invention when the wafer is selectively moved frictionally against the at least two areas by the wafer polishing machine.

Abstract translation: 本发明包括用于晶片抛光机的定制抛光垫。 本发明的抛光垫包括与抛光垫成一体的抛光表面。 抛光表面适于摩擦接触抛光机中的晶片，从而抛光晶片。 抛光垫的抛光表面包括至少两个区域，其中每个区域适于与晶片摩擦接触并实现该区域特有的抛光效果。 当晶片被晶片抛光机选择性地摩擦至少两个区域时，通过本发明的抛光垫来实现定制的抛光效果。