公开(公告)号：US08639914B2

公开(公告)日：2014-01-28

申请号：US13730831

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F15/80

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。

公开(公告)号：US08627053B2

公开(公告)日：2014-01-07

申请号：US12977468

申请日：2010-12-23

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06F9/24 ,  G06F9/40

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F12/1441 ,  G06F12/1491 ,  G06F21/60 ,  G06F21/602 ,  G06F21/78 ,  G06F2221/2107 ,  G06F2221/2125

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract translation: 能够安全执行的处理器。 该处理器包含一个执行单元和安全的分区逻辑，将分区保存在内存中。 处理器还包含耦合到执行单元的加密逻辑，其加密和解密安全数据和代码。

公开(公告)号：US08499012B1

公开(公告)日：2013-07-30

申请号：US12818870

申请日：2010-06-18

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06F12/00 ,  G06F17/30 ,  G06F7/00

CPC classification number: H04L67/1097

Abstract: A system and method are provided for stacking storage drives in a network attached storage (NAS) system. The method provides a NAS stacking network including at least a first and second stackable building block (SBB), where each SBB includes a head, with an embedded processor and storage application, and a storage drive including client files. The method connects a first interface of the first SBB to a client computer device via a LAN switch, and connects a second interface of the first SBB to the first interface of the second SBB. A directory is built of client files stored in the first and second SBBs. The directory is maintained in both the first and second SBBs. In one aspect, the first SBB, acting as a primary SBB, provides access to NAS stacking network directory structure in response to an inquiry from a client computer connected to the LAN switch.

Abstract translation: 提供了一种用于将存储驱动器堆叠在网络连接存储（NAS）系统中的系统和方法。 该方法提供包括至少第一和第二可堆叠构建块（SBB）的NAS堆叠网络，其中每个SBB包括具有嵌入式处理器和存储应用的头部以及包括客户端文件的存储驱动器。 该方法通过LAN交换机将第一SBB的第一接口连接到客户端计算机设备，并将第一SBB的第二接口连接到第二SBB的第一接口。 目录由存储在第一和第二SBB中的客户端文件构建。 该目录保持在第一和第二SBB中。 在一个方面，作为主SBB的第一SBB响应于来自连接到LAN交换机的客户端计算机的查询，提供对NAS堆叠网络目录结构的访问。

公开(公告)号：US08488618B1

公开(公告)日：2013-07-16

申请号：US12769540

申请日：2010-04-28

Applicant: Millind Mittal ,  Robert James Fanfelle

Inventor： Millind Mittal ,  Robert James Fanfelle

IPC: H04L12/28

CPC classification number: H04L63/02 ,  H04L63/0236

Abstract: A system and method provide both inline services and in-network services for a dual-connect service box interposed between a modem and a router. The method transceives communications between a service box wide area network (WAN) port and a local area network (LAN) port of a WAN-connected broadband modem, and between a service box WAN-proxy port and a WAN port of a router. The method also selectively transceives communications between the service box WAN port and a LAN port. A service box binding module monitors messages transceived between the router and the modem to determine the service box WAN IP address, and registers at least one service box WAN IP addresses with a WAN network-connected account server. The method selectively transceives communications in response to an authentification means, which may be identifying an authorized port number in the communications, or identifying an authorized command in the communications.

Abstract translation: 系统和方法为插入在调制解调器和路由器之间的双连接服务盒提供内联服务和网络内服务。 该方法收发WAN连接宽带调制解调器的服务盒广域网（WAN）端口和局域网（LAN）端口之间以及路由器的服务盒WAN代理端口和WAN端口之间的通信。 该方法还选择性地收发服务盒WAN端口和LAN端口之间的通信。 服务箱绑定模块监视路由器和调制解调器之间收发的消息，以确定服务箱WAN IP地址，并向WAN网络连接的帐户服务器注册至少一个服务箱WAN IP地址。 所述方法响应于认证装置选择性地收发通信，所述认证装置可能是识别通信中的授权端口号，或者识别通信中的授权命令。

公开(公告)号：US20130124833A1

公开(公告)日：2013-05-16

申请号：US13730846

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

公开(公告)号：US20130117540A1

公开(公告)日：2013-05-09

申请号：US13730832

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。

公开(公告)号：US08347072B2

公开(公告)日：2013-01-01

申请号：US12977459

申请日：2010-12-23

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06F9/00 ,  H04L9/32

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F12/1441 ,  G06F12/1491 ,  G06F21/60 ,  G06F21/602 ,  G06F21/78 ,  G06F2221/2107 ,  G06F2221/2125

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

公开(公告)号：US20120216018A1

公开(公告)日：2012-08-23

申请号：US13456761

申请日：2012-04-26

Applicant: Alexander D. Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

Inventor： Alexander D. Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

IPC: G06F15/76 ,  G06F9/302

CPC classification number: G06F7/60 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5324 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06F15/7817 ,  G06F17/10 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

公开(公告)号：US07509367B2

公开(公告)日：2009-03-24

申请号：US10861167

申请日：2004-06-04

Applicant: Alexander D. Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

Inventor： Alexander D. Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

IPC: G06F7/38

CPC classification number: G06F7/60 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5324 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06F15/7817 ,  G06F17/10 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

公开(公告)号：US20090024643A1

公开(公告)日：2009-01-22

申请号：US12190692

申请日：2008-08-13

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06F17/30

CPC classification number: G06F17/30961 ,  Y10S707/99942 ,  Y10S707/99943

Abstract: A lookup is performed using multiple levels of compressed stride tables in a multi-bit Trie structure. An input lookup key is divided into several strides including a current stride of S bits. A valid entry in a current stride table is located by compressing the S bits to form a compressed index of D bits into the current stride table. A compression function logically combines the S bits to generate the D compressed index bits. An entry in a prior-level table points to the current stride table and has a field indicating which compression function and mask to use. Compression functions can include XOR, shifts, rotates, and multi-bit averaging. Rather than store all 2S entries, the current stride table is compressed to store only 2D entries. Ideally, the number of valid entries in the current stride table is between 2D−1 and 2D for maximum compression. Storage requirements are reduced.

Abstract translation: 在多位Trie结构中使用多级压缩步幅表进行查找。 输入查找键被分成包括S位的当前步幅的几个步骤。 通过压缩S位来形成当前步幅表中的有效条目，以形成D位的压缩索引到当前步幅表中。 压缩函数逻辑组合S位以产生D压缩索引位。 前一级表中的条目指向当前步幅表，并具有指示要使用的压缩函数和掩码的字段。 压缩功能可以包括XOR，移位，旋转和多位平均。 而不是存储所有2S条目，当前步幅表被压缩以仅存储2D条目。 理想情况下，当前步幅表中有效条目的数量在2D-1和2D之间用于最大压缩。 存储要求降低。