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    Vertical memory devices and methods of manufacturing the same
    1.
    发明授权
    Vertical memory devices and methods of manufacturing the same 有权
    垂直存储器件及其制造方法

    公开(公告)号：US09431418B2

    公开(公告)日：2016-08-30

    申请号：US14697655

    申请日：2015-04-28

    申请人： Won-Seok Jung ,  Chang-Seok Kang ,  Min-Yong Lee ,  Sang-Woo Jin

    发明人： Won-Seok Jung ,  Chang-Seok Kang ,  Min-Yong Lee ,  Sang-Woo Jin

    IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

    摘要： A vertical memory device and a method of manufacturing a vertical memory device are disclosed. The vertical memory device includes a substrate, a plurality of channels, a charge storage structure, a plurality of gate electrodes, a first semiconductor structure, and a protection layer pattern. The substrate includes a first region and a second region. The plurality of channels is disposed in the first region. The plurality of channels extends in a first direction substantially perpendicular to a top surface of the substrate. The charge storage structure is disposed on a sidewall of each channel. The plurality of gate electrodes is arranged on a sidewall of the charge storage structure and is spaced apart from each other in the first direction. The first semiconductor structure is disposed in the second region. The protection layer pattern covers the first semiconductor structure. The protection layer pattern has a thickness substantially similar to a thickness of a lowermost gate electrode.

    摘要翻译： 公开了垂直存储器件和制造垂直存储器件的方法。 垂直存储器件包括衬底，多个通道，电荷存储结构，多个栅电极，第一半导体结构和保护层图案。 衬底包括第一区域和第二区域。 多个通道设置在第一区域中。 多个通道在基本上垂直于基板的顶表面的第一方向上延伸。 电荷存储结构设置在每个通道的侧壁上。 多个栅极布置在电荷存储结构的侧壁上，并且在第一方向上彼此间隔开。 第一半导体结构设置在第二区域中。 保护层图案覆盖第一半导体结构。 保护层图案的厚度基本上类似于最下面的栅电极的厚度。

    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直存储器件及其制造方法

    公开(公告)号：US20150372004A1

    公开(公告)日：2015-12-24

    申请号：US14697655

    申请日：2015-04-28

    申请人： Won-Seok Jung ,  Chang-Seok Kang ,  Min-Yong Lee ,  Sang-Woo Jin

    发明人： Won-Seok Jung ,  Chang-Seok Kang ,  Min-Yong Lee ,  Sang-Woo Jin

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

    摘要： A vertical memory device and a method of manufacturing a vertical memory device are disclosed. The vertical memory device includes a substrate, a plurality of channels, a charge storage structure, a plurality of gate electrodes, a first semiconductor structure, and a protection layer pattern. The substrate includes a first region and a second region. The plurality of channels is disposed in the first region. The plurality of channels extends in a first direction substantially perpendicular to a top surface of the substrate. The charge storage structure is disposed on a sidewall of each channel. The plurality of gate electrodes is arranged on a sidewall of the charge storage structure and is spaced apart from each other in the first direction. The first semiconductor structure is disposed in the second region. The protection layer pattern covers the first semiconductor structure. The protection layer pattern has a thickness substantially similar to a thickness of a lowermost gate electrode.

    摘要翻译： 公开了垂直存储器件和制造垂直存储器件的方法。 垂直存储器件包括衬底，多个通道，电荷存储结构，多个栅电极，第一半导体结构和保护层图案。 衬底包括第一区域和第二区域。 多个通道设置在第一区域中。 多个通道在基本上垂直于基板的顶表面的第一方向上延伸。 电荷存储结构设置在每个通道的侧壁上。 多个栅极布置在电荷存储结构的侧壁上，并且在第一方向上彼此间隔开。 第一半导体结构设置在第二区域中。 保护层图案覆盖第一半导体结构。 保护层图案的厚度基本上类似于最下面的栅电极的厚度。

    Method for implanting ions in semiconductor device
    3.
    发明授权
    Method for implanting ions in semiconductor device 有权
    在半导体器件中注入离子的方法

    公开(公告)号：US08951857B2

    公开(公告)日：2015-02-10

    申请号：US12913267

    申请日：2010-10-27

    申请人： Young-Sun Sohn ,  Seung-Woo Jin ,  Min-Yong Lee ,  Kyoung-Bong Rouh

    发明人： Young-Sun Sohn ,  Seung-Woo Jin ,  Min-Yong Lee ,  Kyoung-Bong Rouh

    IPC分类号： H01L21/8238 ,  H01L21/265

    CPC分类号： H01L21/265 ,  H01L21/26513 ,  H01L21/2658

    摘要： The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate. Other methods for fabricating a semiconductor device improve distribution of transistor parameters across a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile, across the substrate.

    摘要翻译： 本发明提供了用于在半导体器件中注入离子的各种方法，其基本上补偿了在对衬底的整个表面进行均匀离子注入时产生的衬底的中心部分和边缘部分之间的阈值电压的差异。 用于制造半导体器件的其它方法通过形成不均匀的沟道掺杂层或通过在衬底上形成不均匀的结分布来改善晶体管参数跨衬底的分布。

    Method for fabricating a transistor having a recess gate structure
    4.
    发明授权
    Method for fabricating a transistor having a recess gate structure 失效
    一种制造具有凹槽栅结构的晶体管的方法

    公开(公告)号：US07790551B2

    公开(公告)日：2010-09-07

    申请号：US12603906

    申请日：2009-10-22

    申请人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

    发明人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4236 ,  H01L21/26586 ,  H01L21/28061 ,  H01L29/1041 ,  H01L29/516 ,  H01L29/66621

    摘要： A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.

    摘要翻译： 具有凹陷栅极结构的晶体管及其制造方法。 晶体管包括形成在形成在半导体衬底中的第一沟槽的内壁上的栅极绝缘层; 形成在所述栅极绝缘层上以部分地填充所述第一沟槽的栅极导电层; 栅极电极，形成在栅极导电层上，用于完全填充第一沟槽，并被栅极导电层包围; 形成在半导体衬底中的第一沟槽区; 以及形成在半导体衬底的浅部中的源极/漏极区域。

    Method for manufacturing semiconductor memory device using asymmetric junction ion implantation
    5.
    发明授权
    Method for manufacturing semiconductor memory device using asymmetric junction ion implantation 失效
    使用不对称结离子注入制造半导体存储器件的方法

    公开(公告)号：US07687350B2

    公开(公告)日：2010-03-30

    申请号：US11450816

    申请日：2006-06-09

    申请人： Min Yong Lee ,  Kyoung Bong Rouh ,  Seung Woo Jin

    发明人： Min Yong Lee ,  Kyoung Bong Rouh ,  Seung Woo Jin

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/1037 ,  H01L29/66621 ,  H01L29/66659

    摘要： A method for manufacturing a semiconductor memory device using asymmetric junction ion implantation, including performing ion implantation for adjusting a threshold voltage to a semiconductor substrate, forming a gate stack on the semiconductor substrate to define a storage node junction region and a bit line junction region, implanting a first conductive impurity ion and a second conductive impurity ion using a mask layer pattern covering the storage node junction region while exposing the bit line junction region, forming a gate spacer layer at both sides of the gate stack, and implanting the first conductive impurity ion using the gate stack and the gate spacer layer as an ion implantation mask layer to form a storage node junction region and a bit line junction region having different impurity concentrations, and different junction depths from each other.

    摘要翻译： 一种制造使用非对称结离子注入的半导体存储器件的方法，包括执行用于调整对半导体衬底的阈值电压的离子注入，在半导体衬底上形成栅叠层以限定存储节点结区域和位线结区域， 使用覆盖存储节点结区域的掩模层图案注入第一导电杂质离子和第二导电杂质离子，同时暴露位线结区域，在栅极堆叠的两侧形成栅极间隔层，以及注入第一导电杂质 使用栅极堆叠和栅极间隔层作为离子注入掩模层，以形成具有不同杂质浓度和不同结深度的存储节点结区域和位线结区域。

    Partial ion implantation apparatus and method using bundled beam
    7.
    发明申请
    Partial ion implantation apparatus and method using bundled beam 有权
    部分离子注入装置和使用捆束的方法

    公开(公告)号：US20080128640A1

    公开(公告)日：2008-06-05

    申请号：US11445643

    申请日：2006-06-01

    申请人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

    发明人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

    IPC分类号： H01J37/08

    CPC分类号： H01J37/3172 ,  H01J37/045 ,  H01J2237/30472 ,  H01J2237/31703 ,  H01J2237/31708

    摘要： An ion implantation apparatus comprises an ion beam source for generating an initial ion beam, a bundled ion beam generator adapted to change the initial ion beam into a bundled ion beam based on a predetermined frequency to pass the bundled ion beam for a first time while passing the initial ion beam for a second time, a beam line for accelerating the ion beam having passed through the ion beam generator, and an end station for arranging a wafer therein to allow the ion beam accelerated by the beam line to be implanted in the wafer, the end station operating to move the wafer in a direction perpendicular to an ion beam implantation direction, so as to implant the bundled ion beam in a first region of the wafer and the initial ion beam in a second region of the wafer.

    摘要翻译： 离子注入装置包括用于产生初始离子束的离子束源，捆扎离子束发生器，其适于基于预定频率将初始离子束改变成束状离子束，以在经过第一次时通过束状离子束 初始离子束第二次，用于加速已经通过离子束发生器的离子束的束线，以及用于在其中布置晶片以使由束线加速的离子束被植入晶片的终端站 ，所述终端站操作以沿垂直于离子束注入方向的方向移动所述晶片，以将所述束状离子束注入所述晶片的第一区域中，并将所述初始离子束注入所述晶片的第二区域。

    Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same
    8.
    发明授权
    Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same 有权
    具有凹陷栅极和非对称掺杂剂区域的半导体器件及其制造方法

    公开(公告)号：US07332772B2

    公开(公告)日：2008-02-19

    申请号：US11292381

    申请日：2005-11-29

    申请人： Kyoung Bong Rouh ,  Seung Woo Seung ,  Min Yong Lee

    发明人： Kyoung Bong Rouh ,  Seung Woo Seung ,  Min Yong Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7834 ,  H01L29/66621 ,  H01L29/66636

    摘要： A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on the semiconductor such that the gate stack protrudes from the surface of the semiconductor substrate while the gate stack fills the trench, and first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.

    摘要翻译： 具有凹入栅极和不对称掺杂区域的半导体器件包括具有第一侧壁和第二侧壁的沟槽的半导体衬底，其高度彼此不同，设置在半导体衬底上的栅极绝缘层图案， 设置在所述半导体上的栅极堆叠，使得所述栅极堆叠在所述栅极堆叠填充所述沟槽的同时从所述半导体衬底的表面突出;以及设置在所述半导体衬底的与所述第一和第二侧壁相邻的所述上部的第一和第二掺杂剂区域 分别使得第一和第二掺杂剂区域具有不同的步骤。