公开(公告)号：US08705602B1

公开(公告)日：2014-04-22

申请号：US12580587

申请日：2009-10-16

申请人： Weiqi Ding ,  Mengchi Liu ,  Mingde Pan ,  Thungoc M. Tran ,  Sergey Shumarayev

发明人： Weiqi Ding ,  Mengchi Liu ,  Mingde Pan ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC分类号： H03H7/30 ,  H03H7/40

CPC分类号： H04L25/03038 ,  H04L25/03343

摘要： Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).

摘要翻译： 例如，用于串行数字数据信号的发射机均衡器电路包括用于输出通过延迟线电路传播的信号的多个不同延迟版本的抽头延迟线电路。 均衡器电路还包括多个电流数模转换器（“DAC”）。 均衡器电路还包括可控（例如，可编程）路由电路，用于可选地将信号的延迟版本路由到各​​种DAC。 各种DAC所使用的电流强度也优选是可控的（例如，可编程的）。

公开(公告)号：US20120274359A1

公开(公告)日：2012-11-01

申请号：US13540410

申请日：2012-07-02

申请人： Weiqi Ding ,  Mingde Pan

发明人： Weiqi Ding ,  Mingde Pan

IPC分类号： H03K5/22

CPC分类号： H03K3/356139 ,  H03K5/08

摘要： A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

摘要翻译： 高速差分比较器电路具有精确可调的阈值电压。 提供差分参考电压信号来控制比较器的阈值电压。 参考信号的共模电压优选地跟踪由比较器电路正在处理的差分高速串行数据信号的共模电压。

公开(公告)号：US06351485B1

公开(公告)日：2002-02-26

申请号：US09149770

申请日：1998-09-08

申请人： Zaw M. Soe ,  Ewunnet Gebre-Selassie ,  Mingde Pan

发明人： Zaw M. Soe ,  Ewunnet Gebre-Selassie ,  Mingde Pan

IPC分类号： H04B169

CPC分类号： H03L7/095 ,  H03B23/00 ,  H03L7/0891 ,  H03L7/197 ,  H04B1/69

摘要： A spread spectrum modulation technique uses digital control logic to switch back and forth between two feedback divider ratios so that the PLL spreads output clock frequency between two limits determined by the ratios. The spread spectrum control logic can be integrated into any PLL frequency synthesizer.

摘要翻译： 扩频调制技术使用数字控制逻辑在两个反馈分频比之间来回切换，使得PLL将输出时钟频率扩展到由比率确定的两个极限之间。 扩频控制逻辑可以集成到任何PLL频率合成器中。

公开(公告)号：US20130195155A1

公开(公告)日：2013-08-01

申请号：US13363098

申请日：2012-01-31

申请人： Mingde PAN ,  Weiqi DING ,  Sergey SHUMARAYEV ,  Peng LI ,  Masashi SHIMANOUCHI

发明人： Mingde PAN ,  Weiqi DING ,  Sergey SHUMARAYEV ,  Peng LI ,  Masashi SHIMANOUCHI

IPC分类号： H04L25/10 ,  H04B1/38

CPC分类号： H04L25/4917 ,  H03D1/00 ,  H04L25/066 ,  H04L27/06

摘要： One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及用于多电平振幅信令的接收机电路，其包括用于每个符号周期的至少三个幅度电平。 接收器电路包括峰值检测器，参考电压发生器和比较器电路。 峰值检测器被设置为检测多电平幅度信号的峰值电压，并且参考电压发生器使用峰值电压来产生多个参考电压。 比较器电路使用多个参考电压来检测多电平幅度信号的幅度电平。 还公开了其它实施例和特征。

公开(公告)号：US08248107B2

公开(公告)日：2012-08-21

申请号：US12722319

申请日：2010-03-11

申请人： Weiqi Ding ,  Mingde Pan

发明人： Weiqi Ding ,  Mingde Pan

IPC分类号： H03F3/45

CPC分类号： H03K3/356139 ,  H03K5/08

摘要： A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

摘要翻译： 高速差分比较器电路具有精确可调的阈值电压。 提供差分参考电压信号来控制比较器的阈值电压。 参考信号的共模电压优选地跟踪由比较器电路正在处理的差分高速串行数据信号的共模电压。

公开(公告)号：US07999588B1

公开(公告)日：2011-08-16

申请号：US12551434

申请日：2009-08-31

申请人： Mingde Pan ,  Shou-Po Shih ,  Mei Luo ,  Weiqi Ding

发明人： Mingde Pan ,  Shou-Po Shih ,  Mei Luo ,  Weiqi Ding

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes a storage circuit coupled to receive a data signal, a clock input signal and a reset signal. The storage circuit may be used to generate a clock signal. The reset signal is supplied by a reset circuit. The reset circuit may include one or more logic gates to generate the reset signal. The reset circuit receives a phase shifted version of the clock input signal and the reset signal is generated based on the phase shifted version of the clock input signal. In one embodiment, the reset signal is a series of pulses generated at specific intervals to shift the output of the storage circuit from logic high level to logic low level.

摘要翻译： 公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合以接收数据信号，时钟输入信号和复位信号的存储电路。 存储电路可用于产生时钟信号。 复位信号由复位电路提供。 复位电路可以包括一个或多个逻辑门以产生复位信号。 复位电路接收时钟输入信号的相移版本，并且基于时钟输入信号的相移版本产生复位信号。 在一个实施例中，复位信号是以特定间隔产生的一系列脉冲，以将存储电路的输出从逻辑高电平转换到逻辑低电平。

公开(公告)号：US08750406B2

公开(公告)日：2014-06-10

申请号：US13363098

申请日：2012-01-31

申请人： Mingde Pan ,  Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Masashi Shimanouchi

发明人： Mingde Pan ,  Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Masashi Shimanouchi

IPC分类号： H04L25/34 ,  H04L25/49

CPC分类号： H04L25/4917 ,  H03D1/00 ,  H04L25/066 ,  H04L27/06

摘要： One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及用于多电平振幅信令的接收机电路，其包括用于每个符号周期的至少三个幅度电平。 接收器电路包括峰值检测器，参考电压发生器和比较器电路。 峰值检测器被设置为检测多电平幅度信号的峰值电压，并且参考电压发生器使用峰值电压来产生多个参考电压。 比较器电路使用多个参考电压来检测多电平幅度信号的幅度电平。 还公开了其它实施例和特征。

公开(公告)号：US08610466B2

公开(公告)日：2013-12-17

申请号：US13540410

申请日：2012-07-02

申请人： Weiqi Ding ,  Mingde Pan

发明人： Weiqi Ding ,  Mingde Pan

IPC分类号： H03K5/22

CPC分类号： H03K3/356139 ,  H03K5/08

摘要： A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

摘要翻译： 高速差分比较器电路具有精确可调的阈值电压。 提供差分参考电压信号来控制比较器的阈值电压。 参考信号的共模电压优选地跟踪由比较器电路正在处理的差分高速串行数据信号的共模电压。

公开(公告)号：US08451883B1

公开(公告)日：2013-05-28

申请号：US12630674

申请日：2009-12-03

申请人： Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

发明人： Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

IPC分类号： H04B3/46

CPC分类号： G01R31/3171 ,  H04L1/0061 ,  H04L1/203 ,  H04L1/205 ,  H04L1/248 ,  H04L7/033 ,  H04L7/0334 ,  H04L7/048

摘要： Systems, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with an equalized serial input signal. The device may include an equalizer and eye viewer circuitry. The equalizer may receive and perform equalization on a serial input signal to produce the equalized serial input signal, and the eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the equalized serial input signal.

摘要翻译： 提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和装置。 例如，集成电路设备的一个实施例可能能够确定与均衡的串行输入信号相关联的眼图。 该装置可以包括均衡器和眼睛观察器电路。 均衡器可以在串行输入信号上接收和执行均衡以产生均衡的串行输入信号，并且眼睛观察器电路可以确定与均衡的串行输入信号相关联的眼图的水平和垂直边界。

公开(公告)号：US08433958B2

公开(公告)日：2013-04-30

申请号：US12884923

申请日：2010-09-17

申请人： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

发明人： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

IPC分类号： G06F11/00

CPC分类号： H04L1/203 ,  G01R31/3171

摘要： An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

摘要翻译： 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。