公开(公告)号：US06380058B2

公开(公告)日：2002-04-30

申请号：US09263942

申请日：1999-03-08

申请人： Seiji Manabe ,  Mitsuo Kimoto

发明人： Seiji Manabe ,  Mitsuo Kimoto

IPC分类号： H01L2144

CPC分类号： H01L21/2855 ,  C23C14/046 ,  H01L21/76843 ,  H01L21/76844

摘要： A barrier layer is formed at a bottom portion, for example, of a through hole. The thickness of the barrier layer at an upper area, for example, of the through hole is made uniform. The method of manufacturing a semiconductor device includes the steps of: forming a barrier layer by sputtering on a main surface of a silicon substrate while maintaining a first distance between a main surface of the target and the main surface of the silicon substrate; and forming a titanium nitride layer by sputtering on and adjacent to a titanium nitride layer by scattering a target material while maintaining a second distance longer than the first distance between the main surface of the target and the main surface of the silicon substrate.

摘要翻译： 阻挡层形成在例如通孔的底部。 例如通孔的上部区域的阻挡层的厚度均匀。 制造半导体器件的方法包括以下步骤：通过溅射在硅衬底的主表面上形成阻挡层，同时保持靶的主表面和硅衬底的主表面之间的第一距离; 以及通过溅射目标材料而在氮化钛层上和邻近氮化钛层上溅射形成氮化钛层，同时保持比目标主表面和硅衬底主表面之间的第一距离更长的第二距离。

公开(公告)号：US20070238321A1

公开(公告)日：2007-10-11

申请号：US11733316

申请日：2007-04-10

申请人： Takuya Futase ,  Hideaki Tsugane ,  Mitsuo Kimoto ,  Hidenori Suzuki

发明人： Takuya Futase ,  Hideaki Tsugane ,  Mitsuo Kimoto ,  Hidenori Suzuki

IPC分类号： B08B6/00

CPC分类号： H01L21/67184 ,  H01L21/02057 ,  H01L21/02068 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/906

摘要： Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.

摘要翻译： 提供一种制造半导体器件的方法。 在将半导体晶片放置在配备有成膜装置的干洗室的晶片台上之后，用还原气体在半导体晶片的表面上进行干洗处理。 然后，通过使用保持在180℃的喷淋头，在100〜150℃的第一温度下对半导体晶片进行热处理。然后将半导体晶片真空转移到热处理室，其中半导体晶片为 在150-400℃的第二温度下进行热处理。因此，去除了残留在半导体晶片的主表面上的产物。 本发明通过减少硅化镍层的电性能的变化，可以制造具有提高的可靠性和生产率的半导体器件。

公开(公告)号：US07566662B2

公开(公告)日：2009-07-28

申请号：US11733316

申请日：2007-04-10

申请人： Takuya Futase ,  Hideaki Tsugane ,  Mitsuo Kimoto ,  Hidenori Suzuki

发明人： Takuya Futase ,  Hideaki Tsugane ,  Mitsuo Kimoto ,  Hidenori Suzuki

IPC分类号： H01L21/306

CPC分类号： H01L21/67184 ,  H01L21/02057 ,  H01L21/02068 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/906

摘要： Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.

摘要翻译： 提供一种制造半导体器件的方法。 在将半导体晶片放置在配备有成膜装置的干洗室的晶片台上之后，用还原气体在半导体晶片的表面上进行干洗处理。 然后，通过使用保持在180℃的喷淋头，在100〜150℃的第一温度下对半导体晶片进行热处理。然后将半导体晶片真空转移到热处理室，其中半导体晶片为 在150-400℃的第二温度下进行热处理。因此，去除了残留在半导体晶片的主表面上的产物。 本发明通过减少硅化镍层的电性能的变化，可以制造具有提高的可靠性和生产率的半导体器件。

公开(公告)号：US06599820B1

公开(公告)日：2003-07-29

申请号：US09695223

申请日：2000-10-25

申请人： Yasuhiro Kanda ,  Mitsuo Kimoto ,  Kazuyoshi Maekawa ,  Noboru Sekiguchi

发明人： Yasuhiro Kanda ,  Mitsuo Kimoto ,  Kazuyoshi Maekawa ,  Noboru Sekiguchi

IPC分类号： H01L214763

CPC分类号： H01L21/2855 ,  H01L21/28061 ,  H01L29/4941

摘要： A method of producing a semiconductor device having a polymetal wiring structure fabricated by a polycrystalline silicon film, a reaction preventing film, and a tungsten film comprising steps of forming a polycrystalline silicon film 4 and a tungsten nitride film 13 on a silicon substrate 1; forming a tungsten film 14 using a target of tungsten containing fluorine of 10 ppm or less by a sputtering method; and forming a gate electrode 15 by patterning a polycrystalline silicon film 4, the tungsten nitride film 13, and the tungsten film 14, whereby a content of fluorine can be reduced, a film separation is prevented, and a preferable transistor property is obtainable.

摘要翻译： 一种制造具有由多晶硅膜，防反射膜和钨膜制成的多金属配线结构的半导体器件的方法，包括在硅衬底1上形成多晶硅膜4和氮化钨膜13的步骤; 通过溅射法使用含氟量为10ppm以下的钨的目标来形成钨膜14; 以及通过图案化多晶硅膜4，氮化钨膜13和钨膜14来形成栅电极15，从而可以降低氟含量，防止膜分离，并且可以获得优选的晶体管性质。

公开(公告)号：US06304001B1

公开(公告)日：2001-10-16

申请号：US09280649

申请日：1999-03-29

申请人： Noboru Sekiguchi ,  Kimio Hagi ,  Mitsuo Kimoto

发明人： Noboru Sekiguchi ,  Kimio Hagi ,  Mitsuo Kimoto

IPC分类号： H01L23544

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： The semiconductor device with the alignment mark includes a convex portion as a film growth control region for forming side surfaces approximately parallel to sidewalls on surfaces opposite to the sidewalls of first metal interconnection layer formed in a recess portion of the alignment mark at the time of deposition of first metal interconnection layer. Thus, the semiconductor device with the alignment mark and manufacturing method thereof allowing the easy and accurate detection of the location of a layer deposited on side surfaces of the alignment mark can be provided.

摘要翻译： 具有对准标记的半导体器件包括作为膜生长控制区域的凸部，用于在沉积时形成在对准标记的凹部中的形成在第一金属互连层的侧壁的相反侧的表面上大致平行的侧表面 的第一金属互连层。 因此，可以提供具有对准标记的半导体器件及其制造方法，其容易且准确地检测沉积在对准标记的侧表面上的层的位置。