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公开(公告)号：US08912992B2
公开(公告)日：2014-12-16
申请号：US13437038
申请日：2012-04-02
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0205 , G09G2310/08
摘要： A display device includes a driving circuit that applies an active potential which is a potential for turning on pixel transistors sequentially to a plurality of output signal lines, wherein the driving circuit includes a main driving circuit that outputs the active potential to one end of the output signal line of the plurality of output signal lines by applying a clock signal caused by a input of the active potential output from the upper output signal line, and an auxiliary driving circuit that has an auxiliary transistor which is a transistor where the other end of the output signal line is connected to a signal line for the clock signal via the source or the drain. Thereby, output waveform distortion in the scanning signal line can be improved and thus display quality can be enhanced.
摘要翻译： 显示装置包括：驱动电路，其施加作为使像素晶体管顺序地接通到多个输出信号线的电位的有效电位，其中，所述驱动电路包括将所述有源电位输出到所述输出的一端的主驱动电路 通过施加由从上部输出信号线输出的有效电位的输入引起的时钟信号，以及具有作为晶体管的辅助晶体管的辅助晶体管的多个输出信号线的信号线， 输出信号线通过源极或漏极连接到时钟信号的信号线。 由此，能够提高扫描信号线的输出波形失真，能够提高显示质量。
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公开(公告)号：US08638284B2
公开(公告)日：2014-01-28
申请号：US12761423
申请日：2010-04-16
申请人： Yoshihiro Kotani , Mitsuru Goto
发明人： Yoshihiro Kotani , Mitsuru Goto
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G11C19/184 , G11C19/28
摘要： A gate signal line driving circuit and a display device which can suppress the degradation of an element attributed to the use of the element for a long time, and can realize the prolongation of lifetime of the element are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected in parallel, and at least some of the plurality of elements are driven by switching elements.
摘要翻译： 提供了能够长时间抑制归因于元件的元素的劣化的栅极信号线驱动电路和显示装置，并且可以实现元件的使用寿命的延长。 对于长时间施加高电压的元件，多个元件并联连接，并且多个元件中的至少一些元件由开关元件驱动。
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公开(公告)号：US20120327050A1
公开(公告)日：2012-12-27
申请号：US13603935
申请日：2012-09-05
申请人： Mitsuru GOTO , Hiroko Hayata
发明人： Mitsuru GOTO , Hiroko Hayata
IPC分类号： G09G5/00
CPC分类号： G02F1/13454 , G02F1/133617 , G02F1/13452 , G02F1/1362 , G09G3/3611 , G09G3/3614 , G09G3/3648 , G09G3/3688 , G09G2310/027 , G09G2310/0289 , G09G2310/0297
摘要： A display device includes a TFT substrate with gate signal lines, drain signal lines, thin-film transistors connected thereto, a gate driver connected to the gate signal lines, a drain driver having output terminals connected to drain signal lines, and a film substrate having first wirings. The first wirings are disposed between the drain driver and the film substrate. The drain driver is mounted on the film substrate, and the output terminals are connected to the first wirings between the film substrate and the drain driver. The output terminal includes first group terminals formed in parallel with a longer edge of the drain driver, and second group terminals formed in parallel with the longer edge and disposed between the loner edge and the first group terminals.
摘要翻译： 显示装置包括具有栅极信号线的TFT基板，漏极信号线，与其连接的薄膜晶体管，连接到栅极信号线的栅极驱动器，具有连接到漏极信号线的输出端子的漏极驱动器，以及具有 第一条布线 第一配线设置在漏极驱动器和薄膜基板之间。 漏极驱动器安装在薄膜基板上，并且输出端子连接到薄膜基板和漏极驱动器之间的第一布线。 输出端子包括与漏极驱动器的较长边缘平行地形成的第一组端子，以及与较长边缘平行地形成并且设置在孤立边缘和第一组端子之间的第二组端子。
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公开(公告)号：US20120194574A1
公开(公告)日：2012-08-02
申请号：US13442066
申请日：2012-04-09
IPC分类号： G09G5/02
CPC分类号： G09G3/3696 , G09G3/3614 , G09G3/3688 , G09G2310/027 , G09G2310/0289
摘要： A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.
摘要翻译： 一种半导体集成电路，包括锁存显示数据的第一寄存器，根据第一时钟锁存第一寄存器的显示数据的第二寄存器，输出多个灰度级电压的灰度级电压发生器，选择 根据来自多个灰度级电压的第二寄存器的显示数据的灰度级电压，以及包括第一晶体管和第二晶体管的放大器。 第一晶体管的第一端子和第二晶体管的第一端子连接到第一电压线，并且从解码器输出的灰度电压根据第一晶体管的第一端子被提供给第一晶体管和第二晶体管的输入端 一个控制信号。 控制信号的相位以两条水平扫描线的间隔反转。
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公开(公告)号：US20120075282A1
公开(公告)日：2012-03-29
申请号：US13239789
申请日：2011-09-22
IPC分类号： G09G5/00
CPC分类号： G09G3/3677
摘要： In a unit drive circuit in each stage in a shift register, a transistor which is maintained in ON state during a period where the unit drive circuit in the stage does not perform an outputting operation is configured not to generate Vth shift. As switches, transistors T6A, T6B are connected between the output terminal OUT and AC power sources VA, VB. At least one of T6A, T6B is brought into ON state and T6A, T6B are alternately brought into OFF state during the period other than the outputting operation period. VA, VB supply L level during a period where T6A, T6B are in ON state, while VA, VB supply a ground potential GND which is an intermediate potential between an H level and an L level during a period where T6A, T6B are in OFF state.
摘要翻译： 在移位寄存器的各级的单位驱动电路中，在阶段的单位驱动电路不执行输出动作的期间内保持导通状态的晶体管被构成为不产生Vth偏移。 作为开关，晶体管T6A，T6B连接在输出端子OUT和AC电源VA，VB之间。 T6A，T6B中的至少一个变为导通状态，并且在输出操作期间以外的期间，T6A，T6B交替进入截止状态。 VA，VB在T6A，T6B处于导通状态的期间供给L电平，而在V6B，T6B为OFF的期间，VA，VB提供作为H电平和L电平之间的中间电位的地电位GND 州。
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公开(公告)号：US20110292016A1
公开(公告)日：2011-12-01
申请号：US13067280
申请日：2011-05-20
申请人： Yoshinori Aoki , Mitsuru Goto , Shouji Nagao , Kouichi Kotera
发明人： Yoshinori Aoki , Mitsuru Goto , Shouji Nagao , Kouichi Kotera
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G3/20 , G09G3/2003 , G09G3/2011 , G09G3/3696 , G09G5/008 , G09G2310/027 , G09G2310/0278 , G09G2310/08 , G09G2320/0686 , G09G2330/021 , G09G2330/028 , G09G2340/0428 , G11C11/412 , G11C11/417
摘要： The present invention relates to enhancing low power consumption of a display device having a SRAM. The display device includes a drive circuit receiving video data; video lines connected the drive circuit; and pixels connected to the video signals. The drive circuit includes a memory storing the video data in memory cells. Each memory cell includes a first inverter with input and output terminals connected to first and second nodes, respectively. A second inverter has output and input terminals connected to the first and second nodes, respectively. A First and second transistors between a first data line and the first node each have a control terminal connected to a first word line or a third word line, respectively. Third and fourth transistors between a second data line and the second node each have a control terminal connected to a second word line or a fourth word line, respectively.
摘要翻译： 本发明涉及增强具有SRAM的显示装置的低功耗。 显示装置包括：接收视频数据的驱动电路; 视频线连接驱动电路; 和连接到视频信号的像素。 驱动电路包括将视频数据存储在存储单元中的存储器。 每个存储单元包括分别连接到第一和第二节点的输入和输出端子的第一逆变器。 第二反相器分别具有连接到第一和第二节点的输出端和输入端。 第一数据线和第一节点之间的第一和第二晶体管分别具有连接到第一字线或第三字线的控制端。 第二数据线和第二节点之间的第三和第四晶体管分别具有连接到第二字线或第四字线的控制端。
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公开(公告)号：US07990355B2
公开(公告)日：2011-08-02
申请号：US12938736
申请日：2010-11-03
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/3614 , G09G3/3688 , G09G2310/027 , G09G2310/0289
摘要： A semiconductor integrated circuit includes a first register, a second register, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage, and an amplifier including a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor and a first terminal of the second transistors are connected to a first voltage line, a first terminal of the third transistor and a first terminal of the fourth transistor are connected to a second voltage line, a second terminal of the first transistor is connected to a second terminal of the third transistor, and a second terminal of the second transistor is connected to a second terminal of the fourth transistor.
摘要翻译： 半导体集成电路包括第一寄存器，第二寄存器，输出多个灰度级电压的灰度级电压发生器，选择灰度级电压的解码器，以及包括第一晶体管，第二晶体管，第三晶体管的放大器 晶体管和第四晶体管。 第一晶体管的第一端子和第二晶体管的第一端子连接到第一电压线，第三晶体管的第一端子和第四晶体管的第一端子连接到第二电压线，第二端子 第一晶体管连接到第三晶体管的第二端子，第二晶体管的第二端子连接到第四晶体管的第二端子。
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公开(公告)号：US20100302217A1
公开(公告)日：2010-12-02
申请号：US12785800
申请日：2010-05-24
申请人： Takahiro OCHIAI , Mitsuru Goto , Youzou Nakayasu , Yuki Okada , Naoki Takada
发明人： Takahiro OCHIAI , Mitsuru Goto , Youzou Nakayasu , Yuki Okada , Naoki Takada
CPC分类号： G09G3/3696 , G09G3/3674 , G09G2300/0434
摘要： A gate signal line driving circuit which suppresses noises in a gate signal and a display device which uses the gate signal line driving circuit are provided. A first basic circuit provided to a gate signal line driving circuit includes a HIGH voltage applying switching element which applies a HIGH voltage to gate signal lines in response to a signal HIGH period, and a LOW voltage applying switching circuit which applies a LOW voltage to the gate signal lines in response to a signal LOW period. In response to a signal HIGH period, a switch of the LOW voltage applying switching circuit of the first basic circuit is turned off based on a signal applied to a switch of the HIGH voltage applying switching element of a second basic circuit which assumes a signal HIGH period earlier than the first basic circuit.
摘要翻译： 提供了抑制门信号中的噪声的门信号线驱动电路和使用栅信号线驱动电路的显示装置。 提供给栅极信号线驱动电路的第一基本电路包括：高电压施加开关元件，其响应于信号高电平周期向栅极信号线施加HIGH电压;以及低电压施加开关电路，其向所述低电压施加开关元件施加低电压 门信号线响应于信号低电平周期。 响应于信号高电平周期，第一基本电路的低电压施加开关电路的开关基于施加到假设信号为高的第二基本电路的高电压施加开关元件的开关的信号而截止 比第一个基本电路早。
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公开(公告)号：US07830347B2
公开(公告)日：2010-11-09
申请号：US11862433
申请日：2007-09-27
CPC分类号： G09G3/3696 , G09G3/3614 , G09G3/3688 , G09G2310/027 , G09G2310/0289
摘要： A liquid crystal display device includes drain signal lines, gate signal lines, thin film transistors, and a drain driver. The drain driver includes an amplifier circuit having a switching circuit which switches between a first state and a second state, the first state being a state where a first input terminal of the amplifier circuit is coupled to an inverting input terminal and a second input terminal is coupled to a noninverting input terminal, and the second state being a state where the first input terminal is coupled to the noninverting input terminal and the second input terminal is coupled to the inverting input terminal. The amplifier circuit supplies signal voltages to the thin film transistors via the drain signal lines which are gray scale voltages one of plus and minus offset voltages in a first frame and in a second frame.
摘要翻译： 液晶显示装置包括漏极信号线，栅极信号线，薄膜晶体管和漏极驱动器。 漏极驱动器包括具有在第一状态和第二状态之间切换的开关电路的放大器电路，第一状态是放大器电路的第一输入端子耦合到反相输入端子和第二输入端子的状态 耦合到非反相输入端子，并且第二状态是第一输入端子耦合到同相输入端子并且第二输入端子耦合到反相输入端子的状态。 放大器电路经由漏极信号线向薄膜晶体管提供信号电压，漏极信号线是第一帧和第二帧中的正负偏移电压之一的灰度级电压。
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公开(公告)号：US20100265243A1
公开(公告)日：2010-10-21
申请号：US12761423
申请日：2010-04-16
申请人： Yoshihiro KOTANI , Mitsuru Goto
发明人： Yoshihiro KOTANI , Mitsuru Goto
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G11C19/184 , G11C19/28
摘要： A gate signal line driving circuit and a display device which can suppress the degradation of an element attributed to the use of the element for a long time, and can realize the prolongation of lifetime of the element are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected in parallel, and at least some of the plurality of elements are driven by switching elements.
摘要翻译： 提供了能够长时间抑制归因于元件的元素的劣化的栅极信号线驱动电路和显示装置，并且可以实现元件的使用寿命的延长。 对于长时间施加高电压的元件，多个元件并联连接，并且多个元件中的至少一些元件由开关元件驱动。
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