公开(公告)号：US5969413A

公开(公告)日：1999-10-19

申请号：US855931

申请日：1997-05-14

申请人： Keiichi Yano ,  Kazuo Kimura ,  Hironori Asai ,  Jun Monma ,  Koji Yamakawa ,  Mitsuyoshi Endo ,  Hirohisa Osoguchi

发明人： Keiichi Yano ,  Kazuo Kimura ,  Hironori Asai ,  Jun Monma ,  Koji Yamakawa ,  Mitsuyoshi Endo ,  Hirohisa Osoguchi

IPC分类号： H01L23/10 ,  H01L23/15 ,  H01L23/28 ,  H01L23/495 ,  H01L23/02 ,  H01L23/12 ,  H01L23/48

CPC分类号： H01L23/10 ,  H01L23/15 ,  H01L23/49572 ,  H01L24/50 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/30107

摘要： A semiconductor chip is supported on a tape carrier provided with lead wirings. The semiconductor chip is electrically connected to the lead wirings. The semiconductor chip of this quality is bonded in combination with the pe carrier to an aluminum nitride substrate. The lead wirings provided on the carrier combine the two functions as an internal lead and an external lead. The semiconductor package of such a structure as is described above allows multi-terminal connection by the narrowing of pitches between the leads and permits provision of a miniature package excelling in the heat-radiating property. Alternatively, the lead wirings supported on the tape carrier and electrically connected to the semiconductor chip are utilized as internal leads. For the external leads, such lead frames as are bonded to the aluminum nitride substrate are used. The lead frames are electrically connected to the internal leads provided in the tape carrier.

摘要翻译： 半导体芯片被支撑在带有引线配线的带载体上。 半导体芯片电连接到引线配线。 该质量的半导体芯片与pe载体结合到氮化铝衬底上。 载体上提供的导线结合了作为内部引线和外部引线的两个功能。 如上所述的这种结构的半导体封装允许通过引线之间的间距变窄来实现多端子连接，并且允许提供具有优异的散热性能的微型封装。 或者，支撑在带载体上并电连接到半导体芯片的引线配线被用作内部引线。 对于外部引线，使用与氮化铝基板结合的引线框架。 引线框架电连接到设置在带式载体中的内部引线。

公开(公告)号：US4770953A

公开(公告)日：1988-09-13

申请号：US16557

申请日：1987-02-19

申请人： Akihiro Horiguchi ,  Mituo Kasori ,  Fumio Ueno ,  Hideki Sato ,  Nobuyuki Mizunoya ,  Mitsuyoshi Endo ,  Shun-ichiro Tanaka ,  Kazuo Shinozaki

发明人： Akihiro Horiguchi ,  Mituo Kasori ,  Fumio Ueno ,  Hideki Sato ,  Nobuyuki Mizunoya ,  Mitsuyoshi Endo ,  Shun-ichiro Tanaka ,  Kazuo Shinozaki

IPC分类号： C04B41/50 ,  C04B41/51 ,  C04B41/87 ,  C04B41/88 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498 ,  H05K1/09 ,  B32B9/00 ,  C04B35/58

CPC分类号： C04B41/87 ,  C04B41/5053 ,  C04B41/51 ,  C04B41/5133 ,  C04B41/88 ,  H01L21/4846 ,  H01L23/15 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/092 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926

摘要： For higher thermal conductivity, stronger adhesion strength, excellent insulating characteristics, and multilayer interconnection, an aluminium sintered body for circuit substrates comprises a novel conductive metallized layer on the surface of the sintered body. The metallized layer comprises at least one element selected from the first group of Mo, W and Ta and at least one element selected from the second group of IIa, III, IVa group elements, lanthanide elements, and actinide elements in the periodic table, as the conductive phase element. The first group element serves to improve the heat conductivity and resistance, while the second group serves to increase the wetness and adhesion strength between the insulating body and the metallized layer. Further, the plural insulating ceramic bodies and the plural metallized conductive layers can be sintered simultaneously being stacked one above the other to permit a multilayer interconnection.

摘要翻译： 为了更高的导热性，更强的粘合强度，优异的绝缘特性和多层互连，用于电路基板的铝烧结体包括在烧结体表面上的新的导电金属化层。 金属化层包括选自Mo，W和Ta的第一组中的至少一种元素和选自元素周期表中第二组IIa，III，IVa族元素，镧系元素和锕系元素中的至少一种元素，如 导电相元件。 第一组元件用于提高导热性和电阻，而第二组用于增加绝缘体和金属化层之间的湿度和粘合强度。 此外，多个绝缘陶瓷体和多个金属化导电层可以同时被烧结而彼此层叠以允许多层互连。

公开(公告)号：US08766407B2

公开(公告)日：2014-07-01

申请号：US13365516

申请日：2012-02-03

申请人： Mitsuyoshi Endo

发明人： Mitsuyoshi Endo

IPC分类号： H01L29/06

CPC分类号： H01L24/05 ,  H01L21/76256 ,  H01L24/08 ,  H01L2224/05556 ,  H01L2224/05559 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/056 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/8385 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/94 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/053 ,  H01L2924/05442 ,  H01L2924/049 ,  H01L2924/05042

摘要： According to one embodiment, a semiconductor wafer includes a semiconductor substrate and an interconnect layer formed on the semiconductor substrate. In the semiconductor wafer, the semiconductor substrate includes a first region that is located on the outer periphery side of the semiconductor substrate and that is not covered with the interconnect layer. The interconnect layer includes a second region where the upper surface of the interconnect layer is substantially flat. A first insulating film is formed in the first region. The upper surface of the interconnect layer within the second region and the upper surface of the first insulating film substantially flush with each other.

摘要翻译： 根据一个实施例，半导体晶片包括形成在半导体衬底上的半导体衬底和互连层。 在半导体晶片中，半导体衬底包括位于半导体衬底的外周侧并且不被互连层覆盖的第一区域。 互连层包括互连层的上表面基本上平坦的第二区域。 在第一区域形成第一绝缘膜。 第二区域内的互连层的上表面和第一绝缘膜的上表面基本上彼此齐平。

公开(公告)号：US20130049210A1

公开(公告)日：2013-02-28

申请号：US13365516

申请日：2012-02-03

申请人： Mitsuyoshi ENDO

发明人： Mitsuyoshi ENDO

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L21/76256 ,  H01L24/08 ,  H01L2224/05556 ,  H01L2224/05559 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/056 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/8385 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/94 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/053 ,  H01L2924/05442 ,  H01L2924/049 ,  H01L2924/05042

摘要： According to one embodiment, a semiconductor wafer includes a semiconductor substrate and an interconnect layer formed on the semiconductor substrate. In the semiconductor wafer, the semiconductor substrate includes a first region that is located on the outer periphery side of the semiconductor substrate and that is not covered with the interconnect layer. The interconnect layer includes a second region where the upper surface of the interconnect layer is substantially flat. A first insulating film is formed in the first region. The upper surface of the interconnect layer within the second region and the upper surface of the first insulating film substantially flush with each other.

摘要翻译： 根据一个实施例，半导体晶片包括形成在半导体衬底上的半导体衬底和互连层。 在半导体晶片中，半导体衬底包括位于半导体衬底的外周侧并且未被互连层覆盖的第一区域。 互连层包括互连层的上表面基本上平坦的第二区域。 在第一区域形成第一绝缘膜。 第二区域内的互连层的上表面和第一绝缘膜的上表面基本上彼此齐平。

公开(公告)号：US20120248624A1

公开(公告)日：2012-10-04

申请号：US13308826

申请日：2011-12-01

申请人： Mitsuyoshi Endo

发明人： Mitsuyoshi Endo

IPC分类号： H01L23/48 ,  H01L21/302

CPC分类号： H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2224/92132 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

摘要： According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.

摘要翻译： 根据一个实施例，将第一基板的第一后表面和第二基板的第二前表面接合在一起，以将第一导体与第二导体连接。 第一导体包括直径等于在第一金属层和第一前表面之间的范围内形成在第一金属层之上的第一间隙的直径的部分和具有大于第一间隙的直径的部分， 在第一金属层和第一背面之间的范围内小于第一金属层的外径。 第一绝缘层具有形成在第一金属层上方的间隙，该间隙大于第一间隙并小于第一金属层的外径。

公开(公告)号：US20110007448A1

公开(公告)日：2011-01-13

申请号：US12714773

申请日：2010-03-01

申请人： Mitsuyoshi Endo

发明人： Mitsuyoshi Endo

IPC分类号： H01G5/16

CPC分类号： H01G5/16

摘要： A variable capacity element has a substrate, a pair of capacitor electrodes, a pair of driver electrodes, and a pair of capacitor wirings why one of the capacitor electrodes is movable by applying a voltage between the driver electrodes. A pair of driver electrodes are connected to the pair of capacitor electrodes, being insulated from the capacitor electrodes. A pair of capacitor wiring extend in parallel each other from connecting portions with the pairs of the capacitor electrodes, being electrically connected with the capacitor electrodes.

摘要翻译： 可变容量元件具有基板，一对电容器电极，一对驱动电极和一对电容器布线，为什么通过在驱动电极之间施加电压可以使电容器电极之一移动。 一对驱动电极连接到一对电容器电极，与电容器电极绝缘。 一对电容器配线从与电容器电极对的连接部分平行地延伸，与电容器电极电连接。

公开(公告)号：US20120248579A1

公开(公告)日：2012-10-04

申请号：US13238705

申请日：2011-09-21

申请人： Mitsuyoshi ENDO

发明人： Mitsuyoshi ENDO

IPC分类号： H01L29/41 ,  H01L21/30

CPC分类号： H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2224/92132 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

摘要： According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.

公开(公告)号：US20120038029A1

公开(公告)日：2012-02-16

申请号：US13179682

申请日：2011-07-11

申请人： Mitsuyoshi Endo

发明人： Mitsuyoshi Endo

IPC分类号： H01L29/41 ,  H01L21/76

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/014 ,  H01L2224/03

摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, a first insulating layer, an electrode pad, a through hole, a second insulating layer, and a conductive material. A through groove passes through the semiconductor substrate from a surface to an opposite surface. The first insulating layer fills the through groove. The electrode pad is connected with an interconnection layer. The second insulating layer is provided between the electrode pad and the first insulating layer. The through hole communicates with the electrode pad and passes through the first insulating layer and the second insulating layer. The conductive material is provided in the through hole so as to be connected with the electrode pad.

摘要翻译： 根据一个实施例，半导体器件包括半导体衬底，第一绝缘层，电极焊盘，通孔，第二绝缘层和导电材料。 通孔从表面通过半导体衬底到相对表面。 第一绝缘层填充通孔。 电极焊盘与互连层连接。 第二绝缘层设置在电极焊盘和第一绝缘层之间。 通孔与电极焊盘连通并穿过第一绝缘层和第二绝缘层。 导电材料设置在通孔中以与电极焊盘连接。

公开(公告)号：US06861738B2

公开(公告)日：2005-03-01

申请号：US10156819

申请日：2002-05-30

申请人： Katsuhiko Oyama ,  Mitsuyoshi Endo ,  Chiaki Takubo ,  Takashi Yamazaki ,  Takashi Imoto

发明人： Katsuhiko Oyama ,  Mitsuyoshi Endo ,  Chiaki Takubo ,  Takashi Yamazaki ,  Takashi Imoto

IPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L23/02

CPC分类号： H01L23/5382 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16

摘要： There is disclosed a laminated-chip semiconductor device which comprises two chip-mounting substrates on each of which at least one semiconductor chip having a plurality of terminals for signals is mounted, and a plurality of chip connecting wirings electrically connected to the terminals for signals of the each semiconductor chip which are mounted on the chip-mounting substrates are formed in a same pattern, and which are laminated along a thickness direction, and one intermediate substrate which is arranged between the two chip-mounting substrates, and in which a plurality of interlayer connecting wirings electrically connected to each of the plurality of chip connecting wirings of the adjacent chip-mounting substrate are formed in a predetermined wiring pattern.

摘要翻译： 公开了一种层叠芯片半导体器件，其包括两个芯片安装基板，每个芯片安装基板上安装有至少一个具有多个用于信号的端子的半导体芯片，以及电连接到端子的多个芯片连接布线， 安装在芯片安装基板上的每个半导体芯片以相同的图案形成，并且沿着厚度方向层叠，并且一个中间基板被布置在两个芯片安装基板之间，并且其中多个 电连接到相邻芯片安装基板的多个芯片连接布线中的每一个的层间连接布线以预定布线图形形成。

公开(公告)号：US5176309A

公开(公告)日：1993-01-05

申请号：US704094

申请日：1991-05-22

申请人： Akihiro Horiguchi ,  Mitsuo Kasori ,  Fumio Ueno ,  Hiroshi Komorita ,  Mitsuyoshi Endo

发明人： Akihiro Horiguchi ,  Mitsuo Kasori ,  Fumio Ueno ,  Hiroshi Komorita ,  Mitsuyoshi Endo

IPC分类号： H05K1/03 ,  H01L21/48 ,  H05K3/38

CPC分类号： H05K3/38 ,  H01L21/4839 ,  H05K1/0306 ,  H05K2201/0355 ,  Y10T29/49155

摘要： According to this invention, there is provided a method of manufacturing a highly reliable circuit board in which a copper member is strongly, directly bonded to a substrate made of an aluminum nitride sintered body, thereby obtaining high peel strength. The method of manufacturing the circuit board includes the steps of bringing a copper member containing 100 to 1,000 ppm of oxygen into contact with an oxide layer having a thickness of 0.1 to 5 .mu.m formed on a surface of a substrate made of an aluminum nitride sintered body, and heating the substrate in an inert gas atmosphere containing 1 to 100 ppm of oxygen at a temperature not more than a temperature corresponding to a liquidus including a pure copper melting point of a hypoeutectic region of a two-component phase diagram of Cu-Cu.sub.2 O and not less than a temperature corresponding to a eutectic line obtained by connecting a line corresponding to copper and a line corresponding to a cuporus oxide composition, and directly bonding the copper member to the substrate.

摘要翻译： 根据本发明，提供了一种制造高可靠性电路板的方法，其中铜构件牢固地直接接合到由氮化铝烧结体制成的衬底上，从而获得高剥离强度。 制造电路板的方法包括以下步骤：将含有100-1000ppm氧的铜构件与形成在由氮化铝烧结体制成的衬底的表面上形成的厚度为0.1至5μm的氧化物层接触 在含有1〜100ppm氧气的惰性气体气氛中，在不高于对应于包含Cu-Cu的双组分相图的亚共晶层的纯铜熔点的液相线的温度的温度下， 并且不低于对应于通过连接对应于铜的线和对应于氧化铜组合物的线而获得的共晶线的温度，并且将铜构件直接接合到衬底。