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公开(公告)号：US20240365530A1
公开(公告)日：2024-10-31
申请号：US18764368
申请日：2024-07-05
发明人： Tseng-Fu LU , Chuan-Lin HSIAO
IPC分类号： H10B12/00 , H01L21/762 , H01L29/06
CPC分类号： H10B12/315 , H01L21/762 , H01L29/0649 , H10B12/03 , H10B12/482 , H10B12/488
摘要： A memory structure includes a substrate, a first word line and a first word line. The substrate has a plurality of active areas and an isolation structure surrounding the active areas. The first word line trench is formed across a first active area of the active areas and the isolation structure. The first word line trench includes a first slot and a first groove. The first slot is recessed from a top surface of the substrate. The first groove expands from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first groove. A first word line is formed in the first word line trench. The first word line comprises a gate dielectric conformally formed on the first groove and the first slot.
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公开(公告)号：US20240363494A1
公开(公告)日：2024-10-31
申请号：US18765069
申请日：2024-07-05
发明人： LIANG-PIN CHOU
IPC分类号： H01L23/48 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/481 , H01L21/76838 , H01L21/76898 , H01L23/5226 , H01L23/53238
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.
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3.发明公开公开(公告)号：US20240363454A1
公开(公告)日：2024-10-31
申请号：US18239231
申请日：2023-08-29
发明人： WU-DER YANG
CPC分类号： H01L22/32 , G01R31/2884 , H01L21/78 , H01L24/05 , H01L2224/05553
摘要： A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.
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公开(公告)号：US12130592B2
公开(公告)日：2024-10-29
申请号：US18152747
申请日：2023-01-10
发明人： Heng Lin
IPC分类号： G04F10/00 , H03L7/099 , H03M7/30 , H04L27/227
CPC分类号： G04F10/005 , G04F10/00 , H03L7/099 , H03M7/3084 , H04L27/2272
摘要： A time-to-digital converter apparatus and a converting method thereof are provided. An output signal of a first ring oscillator circuit is counted to generate a first digital code. An output signal of a second ring oscillator circuit is counted to generate a second digital code. A corresponding third digital code is generated according to a time point of phase coincidence between one of outputs of a plurality of first delay stages of the first ring oscillator circuit and one of outputs of a plurality of second delay stages of the second ring oscillator circuit.
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公开(公告)号：US12125800B2
公开(公告)日：2024-10-22
申请号：US17683474
申请日：2022-03-01
发明人： Chun-Yen Wei
IPC分类号： H01L23/544 , H01L21/768 , H01L23/522 , H01L21/027 , H01L21/033
CPC分类号： H01L23/544 , H01L21/76802 , H01L23/5226 , H01L21/0274 , H01L21/0337 , H01L2223/54426
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first conductive feature, a first light-emitting feature, a first pattern and a second pattern. The first light-emitting feature is disposed on the substrate. The first pattern is disposed on the first light-emitting feature. The second pattern is disposed on the first pattern. The first conductive feature is disposed on the substrate and at least laterally overlaps the first pattern. The first light-emitting feature is configured to emit a light of a first wavelength. The first pattern has a first transmittance to the light of the first wavelength. The second pattern has a second transmittance to the light of the first wavelength. The first transmittance is different from the second transmittance.
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公开(公告)号：US12125642B2
公开(公告)日：2024-10-22
申请号：US18193653
申请日：2023-03-31
发明人： Chien-Chung Wang , Hsih-Yang Chiu
CPC分类号： H01G4/228 , H01G13/00 , H01L28/91 , H01L28/92 , H01L29/945 , H10B12/038 , H10B12/37 , H10B12/39
摘要： A method of manufacturing a capacitor structure includes the following. A first, second, third, fourth, fifth, sixth and seventh portions of a contact layer arrange from periphery to center. A first-conductive layer contacting the first portion forms in an opening. A first-dielectric layer contacting the second portion forms on the first-conductive layer. A second-conductive layer forms on the first-dielectric layer. A second-dielectric layer contacting the third portion forms on the second-conductive layer. A third-conductive layer contacting the fourth portion forms on the second-dielectric layer. A third-dielectric layer contacting the fifth portion forms on the third-conductive layer. A fourth-conductive layer contacting the second-conductive layer forms on the third-dielectric layer. A fourth-dielectric layer contacting the sixth portion forms on the fourth-conductive layer. A fifth-conductive layer contacting the seventh portion forms on the fourth-dielectric layer. A fifth-dielectric layer forms on the fourth-dielectric layer and the fifth-conductive layer.
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公开(公告)号：US20240347451A1
公开(公告)日：2024-10-17
申请号：US18134529
申请日：2023-04-13
发明人： ZIH-HONG YANG
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522
CPC分类号： H01L23/5283 , H01L21/76804 , H01L21/76831 , H01L21/76877 , H01L23/5226
摘要： An interconnection structure and a method of manufacturing an interconnection structure are provided. The interconnection structure includes a first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first conductive layer disposed in the first dielectric layer. The interconnection structure also includes a conductive via electrically connected with the first conductive layer and extending through the first dielectric layer and the second dielectric layer. The conductive via has a first lateral surface surrounded by the first dielectric layer and a second lateral surface surrounded by the second dielectric layer. The first lateral surface and the second lateral surface have different slopes.
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8.发明公开公开(公告)号：US20240347378A1
公开(公告)日：2024-10-17
申请号：US18133058
申请日：2023-04-11
发明人： YING-CHENG CHUANG
IPC分类号： H01L21/768 , H01L23/528
CPC分类号： H01L21/76802 , H01L21/76837 , H01L23/5283
摘要： The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. A substrate is provided, wherein the substrate includes a plurality of pillars, and a top surface of each of the plurality of pillars is a substantially planar surface. A first oxide layer is formed over the substrate conformal to the pillars, wherein the formation of the first oxide layer includes oxidizing top corners of the pillars, thereby causing the top surface of each of the plurality of pillars to become a convex surface. A first dielectric layer is formed among the pillars, wherein the first oxide layer above the plurality of pillars is partially exposed through the first dielectric layer. A planarization is performed on the pillars to partially or entirely remove the convex surface.
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公开(公告)号：US20240341084A1
公开(公告)日：2024-10-10
申请号：US18744946
申请日：2024-06-17
发明人： CHING-KAI CHUANG
IPC分类号： H10B12/00
CPC分类号： H10B12/37 , H10B12/038
摘要： The present application provides a memory device having a memory cell with reduced protrusion protruding from the memory cell. The memory device includes a semiconductor substrate having a fin portion protruding from a surface of the semiconductor substrate; a semiconductive layer disposed conformal to the fin portion; a conductive layer disposed over the semiconductive layer; an insulating layer disposed over the conductive layer; and a protrusion including a first protruding portion laterally protruding from the semiconductive layer and along the surface, a second protruding portion laterally protruding from the conductive layer and over the first protruding portion, and a third protruding portion laterally protruding from the insulating layer and over the second protruding portion, wherein the protrusion has an undercut profile.
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公开(公告)号：US12114476B2
公开(公告)日：2024-10-08
申请号：US18221534
申请日：2023-07-13
发明人： Yuan-Yuan Lin
IPC分类号： H10B12/00
CPC分类号： H10B12/0335 , H10B12/053 , H10B12/315 , H10B12/34
摘要： A method for preparing the memory are provided. The method includes forming a trench at a front side of a semiconductor substrate, wherein the trench defines laterally separate active areas formed of surface regions of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than top surfaces of the active areas; recessing a first group of the active areas from top surfaces of the first group of the active areas, while having top surfaces of a second group of the active areas covered; and forming contact enhancement sidewall spacers to laterally surround top portions of the active areas, respectively.
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