公开(公告)号：US20230090750A1

公开(公告)日：2023-03-23

申请号：US17802837

申请日：2021-03-09

申请人： Nordic Semiconductor ASA

发明人： Marko WINBLAD ,  Hannu TALVITIE

IPC分类号： H04L9/08 ,  H04L9/32

摘要： An integrated-circuit radio transmitter chip comprises a transmitter, a cryptographic engine and control circuitry for the cryptographic engine. The cryptographic engine performs a cryptographic operation by receiving input data, performing a first process to generate first result data and a second process to generate second result data. The first and second result data are used to generate output data. In response to determining that the transmitter is active, the control circuity controls the cryptographic engine to perform the first process and prevents the cryptographic engine from performing the second process while the transmitter is active. The control circuitry controls the cryptographic engine to perform the second process in response to determining that the transmitter is not active.

公开(公告)号：US11576185B2

公开(公告)日：2023-02-07

申请号：US17255868

申请日：2019-06-20

申请人： Nordic Semiconductor ASA

发明人： Pasi Yliuntinen ,  Mauri Nissilä ,  Hanna-Liisa Tiri

IPC分类号： H04W72/04 ,  H04L1/00 ,  H04W72/0446

摘要： A method of operating a radio receiver to receive downlink control information from a wireless network over a physical downlink control channel, said method comprising receiving a plurality of downlink control information prospect signals; decoding at least one of said prospect signals to produce a prospect sequence; reading a declared repetition level from said prospect sequence; comparing said declared repetition level with a repetition level specified in a predetermined format hypothesis for said downlink control information to determine whether a match exists; if said match exists, storing at least part of said prospect sequence as a prospect stored portion; and subsequently deriving said downlink control information from a prospect stored portion and using said downlink control information in further communications.

公开(公告)号：US20230031301A1

公开(公告)日：2023-02-02

申请号：US17865185

申请日：2022-07-14

申请人： Nordic Semiconductor ASA

发明人： Wei Li ,  Eivind Sjøgren Olsen

IPC分类号： H04W56/00 ,  H04L7/00

摘要： A radio receiver device determines whether a digital radio signal includes a predetermined cyclic preamble. An input portion samples the digital radio signal and generates a plurality of samples for storage in a buffer. A first autocorrelator correlates first and second subsets of the samples to generate a first correlation metric, the second subset having been stored in the buffer earlier than said first subset by an even integer multiple of half of the preamble period. A second autocorrelator correlates first and third subsets of the plurality of samples to generate a second correlation metric, the third subset having been stored in the buffer earlier than said first subset by an odd integer multiple of half of the preamble period. A processing portion calculates a difference between the correlation metrics and determines that the radio signal includes the predetermined cyclic preamble when the difference is greater than a threshold value.

公开(公告)号：US20220377690A1

公开(公告)日：2022-11-24

申请号：US17737672

申请日：2022-05-05

申请人： Nordic Semiconductor ASA

发明人： Wei LI

IPC分类号： H04W56/00

摘要： A radio apparatus is configured to correlate signal data with stored synchronization data to generate synchronization correlation data. The signal data represents a received radio-frequency signal that encodes a data frame having a synchronization preamble comprising a plurality of instances of a predetermined synchronization sequence. The stored synchronization data represents the predetermined synchronization sequence. The synchronization correlation data is generated by correlating signal data representing the synchronization preamble with the stored synchronization data. While generating the synchronization correlation data, the radio apparatus identifies a first set of one or more peaks in the synchronization correlation data, and determines first synchronization information from the first set of one or more peaks. After generating more of the synchronization correlation data, the radio apparatus identifies a second set of one or more peaks in the synchronization correlation data, and determines second synchronization information from the second set of one or more peaks.

公开(公告)号：US20220374383A1

公开(公告)日：2022-11-24

申请号：US17750135

申请日：2022-05-20

申请人： Nordic Semiconductor ASA

发明人： Berend Dekens

IPC分类号： G06F13/42 ,  G06F9/46

摘要： An electronic device comprises a module configured to transfer data bus transactions from a transaction source domain to a transaction target domain. A first interface receives the transaction from the source domain using a transaction source ID. A second interface sends the transaction to the target domain using a transaction target ID. A look-up table has a plurality of index values and stores the transaction source ID against one of the index values. Mapping logic determines whether the look-up table contains the transaction source ID stored against any of the index values. When the transaction source ID is already stored, the transaction target ID is set to that index value. Conversely, when the transaction source ID is not stored, an available index value is selected, the transaction source ID is stored against that available index value, and the transaction target ID is set to that available index value.

公开(公告)号：US20220374374A1

公开(公告)日：2022-11-24

申请号：US17750139

申请日：2022-05-20

申请人： Nordic Semiconductor ASA

发明人： Berend Dekens

IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F13/40 ,  G06F9/46

摘要： An electronic device comprises a bridge configured to transfer data bus transactions from a transaction source domain having a first bus width to a transaction target domain having a second bus width less than the first bus width. The bridge comprises a first interface configured to receive a transaction from the transaction source domain, where the transaction has a first transaction burst length. A converter logic is configured such that when a transaction is received via the first interface, the converter logic splits the transaction into a plurality of second transactions each having a respective second transaction burst length, wherein the plurality of second transactions have the second bus width. A second interface is configured to send the plurality of second transactions to the transaction target domain.

公开(公告)号：US20220360221A1

公开(公告)日：2022-11-10

申请号：US17736004

申请日：2022-05-03

申请人： Nordic Semiconductor ASA

发明人： Harald Garvik

IPC分类号： H03B5/36 ,  H03L7/099

摘要： A method of operating an oscillator circuit comprising a resonator is provided. The method comprises maintaining a resonance of the resonator by a) connecting the resonator to an input voltage (Vbuf) for a first pulse period to charge the resonator only partially towards the input voltage (Vbuf); b) connecting the resonator to a second, lower, voltage for a second pulse period to discharge the resonator at least partially; and repeating steps a) and b) at a rate corresponding to the resonance of the resonator and with a phase corresponding to the resonance of the resonator, so as to maintain the resonance of the resonator.

公开(公告)号：US11467892B2

公开(公告)日：2022-10-11

申请号：US16966179

申请日：2019-01-30

申请人： Nordic Semiconductor ASA

发明人： Anders Nore ,  Joar Rusten ,  Steffen Wiken

IPC分类号： G06F9/54 ,  G06F13/24 ,  G06F1/28 ,  G06F9/4401 ,  G06F13/40

摘要： A semiconductor integrated-circuit device comprises two processing subsystems, each comprising a respective processor, set of local peripherals, and bridge unit, all connected to a respective local bus. An electrical interconnect joins the respective bridge units. The first bridge unit comprises a task register, accessible over the first local bus, and can be configured to detect a write to the task register, and respond by sending an event signal over the interconnect to the second bridge unit. The second bridge unit can be configured to receive the event signal, and respond by sending an interrupt signal to the second processor.

公开(公告)号：US20220310140A1

公开(公告)日：2022-09-29

申请号：US17699813

申请日：2022-03-21

申请人： Nordic Semiconductor ASA

发明人： Jussi TAKKALA

IPC分类号： G11C7/10 ,  G11C7/20

摘要： According to an aspect, there are provided an apparatus and a method for providing an access to a memory circuit. A read enable input initializing a wait state counter configured to count a predetermined number of clock cycles is received (200) and the wait state counter output is monitored. A memory ready signal output is received (202) from the memory circuit at a synchronizer input and the output signal of the synchronizer is monitored. An ON-state data ready signal is provided (204) when either the wait state counter has elapsed, or the output signal of the synchronizer is in ON-state.

公开(公告)号：US11456854B2

公开(公告)日：2022-09-27

申请号：US16968121

申请日：2019-02-14

申请人： Nordic Semiconductor ASA

发明人： Kauko Kutti ,  Jarmo Veikkola ,  Marko Winblad

IPC分类号： H04L9/00 ,  H04L9/06 ,  H04L9/08

摘要： A cryptographic module is switchable between a key-input mode and a data-input mode. In the key-input mode, the cryptographic module receives key data, key length information and first input data, combines an amount of the key data corresponding to the key length information with the first input data to produce combined data, wherein a key-influenced length of the combined data is the shortest length of the combined data that contains every data bit of the combined data whose value depends on the key data. It performs a cryptographic operation on the combined data to generate first output data and does not output any of the first output data until after the cryptographic operation has been applied to all of the key-influenced length of the combined data. In the data-input mode of operation, the cryptographic module receives a quantity of second input data whose length can be less than said key-influenced length, performs the cryptographic operation on the second input data to generate second output data and outputs the second output data.