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    Method and apparatus for fast wake-up of analog biases
    2.
    发明授权
    Method and apparatus for fast wake-up of analog biases 有权
    用于快速唤醒模拟偏差的方法和装置

    公开(公告)号：US08350610B2

    公开(公告)日：2013-01-08

    申请号：US12840691

    申请日：2010-07-21

    Applicant: Praveen Mosalikanti ,  Harishankar Sridharan ,  Jacob Schneider ,  Pushkar Gorur ,  Nasser A. Kurd

    Inventor： Praveen Mosalikanti ,  Harishankar Sridharan ,  Jacob Schneider ,  Pushkar Gorur ,  Nasser A. Kurd

    IPC: H03K3/02

    CPC classification number: H03K17/22 ,  H03K19/0008

    Abstract: Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.

    Abstract translation: 这里描述了以最小延迟来唤醒模拟偏置信号的方法和装置。 该装置包括第一逻辑单元，用于响应于断电事件经由第一预定信号调节门控偏置信号的信号电平; 比较器，用于将门控偏置信号与非门控偏置信号进行比较，并且可操作以产生指示比较结果的输出信号; 以及耦合到所述比较器的自定时逻辑单元，用于响应于所述断电事件和所述输出信号的结束而产生唤醒信号。

    PLL with controllable bias level
    3.
    发明授权
    PLL with controllable bias level 有权
    PLL具有可控偏置电平

    公开(公告)号：US07688150B2

    公开(公告)日：2010-03-30

    申请号：US11564776

    申请日：2006-11-29

    Applicant: Nasser A. Kurd ,  Ravindra B. Venigalla

    Inventor： Nasser A. Kurd ,  Ravindra B. Venigalla

    IPC: H03L1/00

    CPC classification number: H03L7/10 ,  H03L7/099

    Abstract: Embodiments disclosed herein may provide circuits having two or more different supplies to separately power analog and digital components in a circuit. In some embodiments, circuits such as PLLs may be provided with adjustable analog supplies. Other embodiments may be disclosed and/or claimed herein.

    Abstract translation: 本文公开的实施例可以提供具有两个或更多个不同电源的电路，以单独为电路中的模拟和数字组件供电。 在一些实施例中，诸如PLL的电路可以设置有可调节的模拟电源。 本文可以公开和/或要求其他实施例。

    Apparatus for power consumption reduction
    4.
    发明授权
    Apparatus for power consumption reduction 失效
    降低功耗的设备

    公开(公告)号：US07562316B2

    公开(公告)日：2009-07-14

    申请号：US11486030

    申请日：2006-07-14

    Applicant: James W. Tschanz ,  Nasser A. Kurd ,  Javed Barkatullah ,  Vivek K. De

    Inventor： James W. Tschanz ,  Nasser A. Kurd ,  Javed Barkatullah ,  Vivek K. De

    IPC: G06F17/50

    CPC classification number: G06F17/5045

    Abstract: A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.

    Abstract translation: 提供了一种降低功耗的方法和芯片设计。 具有相位逻辑电路的第一功能块可以设置在芯片的第一区域中。 具有边缘触发电路的第二功能块可以设置在芯片的第二区域中。 第二功能块内的边沿触发电路可以用双边沿触发电路代替。 相位逻辑电路可以由全频时钟信号来计时，并且双边沿触发电路可以由半频时钟信号来计时。

    CIRCUIT WITH ADJUSTABLE ANALOG SUPPLY
    5.
    发明申请
    CIRCUIT WITH ADJUSTABLE ANALOG SUPPLY 有权
    具有可调节模拟电源的电路

    公开(公告)号：US20080122550A1

    公开(公告)日：2008-05-29

    申请号：US11564776

    申请日：2006-11-29

    Applicant: Nasser A. Kurd ,  Ravindra B. Venigalla

    Inventor： Nasser A. Kurd ,  Ravindra B. Venigalla

    IPC: H03L7/099

    CPC classification number: H03L7/10 ,  H03L7/099

    Abstract: Embodiments disclosed herein may provide circuits having two or more different supplies to separately power analog and digital componets in a circuit. In some embodiments, circuits such as PLLs may be provided with adjustable analog supplies. Other embodiments may be disclosed and/or claimed herein.

    Abstract translation: 本文公开的实施例可以提供具有两个或更多个不同电源的电路，以单独为电路中的模拟和数字组件供电。 在一些实施例中，诸如PLL的电路可以设置有可调节的模拟电源。 本文可以公开和/或要求其他实施例。

    CLOCK GENERATION SYSTEM
    6.
    发明申请
    CLOCK GENERATION SYSTEM 有权
    时钟发生系统

    公开(公告)号：US20080101523A1

    公开(公告)日：2008-05-01

    申请号：US11553104

    申请日：2006-10-26

    Applicant: NASSER A. KURD ,  Ravindra B. Venigalla

    Inventor： NASSER A. KURD ,  Ravindra B. Venigalla

    IPC: H03D3/24

    CPC classification number: H03L7/23 ,  H03L2207/10

    Abstract: Disclosed herein are clock generator systems comprising first and second stage PLLs thereby allowing for both lower PLL bandwidth filtering and higher bandwidth response, in accordance with some embodiments. Other systems may be disclosed and/or described herein.

    Abstract translation: 本文公开了根据一些实施例的包括第一和第二级PLL的时钟发生器系统，由此允许较低的PLL带宽滤波和较高的带宽响应。 本文可以公开和/或描述其它系统。

    Automated clock alignment for testing processors in a bypass mode
    8.
    发明授权
    Automated clock alignment for testing processors in a bypass mode 失效
    以旁路模式测试处理器的自动时钟对齐

    公开(公告)号：US06704892B1

    公开(公告)日：2004-03-09

    申请号：US09583268

    申请日：2000-05-31

    Applicant: Nasser A. Kurd ,  Javed S. Barkatullah ,  Tim Frodsham ,  David J. O'Brien

    Inventor： Nasser A. Kurd ,  Javed S. Barkatullah ,  Tim Frodsham ,  David J. O'Brien

    IPC: G01R3128

    CPC classification number: G06F11/27 ,  G01R31/31725 ,  G01R31/318594

    Abstract: In a bypass mode, a tester may bypass the core and input/output phase locked loops (PLLs) utilized by a processor to develop internal clock signals. External, tester-generated, phase shifted clock signals may be used to generate aligned high frequency signals to replace those generated by the phase locked loops. A plurality of phase shifted, tester generated clock signals may be subjected to an exclusive OR operation for generating input/output and core clock replacement signals. The clock signals received from the tester may also be aligned. Thus, a variety of skews may be compensated before entering the bypass mode. In some embodiments of the present invention, the core and I/O PLL clocks are used to establish alignment in a set-up phase and in other embodiments, the core and I/O PLL need not be utilized at all to generate appropriate internal clock signals from an external tester.

    Abstract translation: 在旁路模式下，测试人员可以绕过核心和处理器利用的输入/输出锁相环（PLL）来开发内部时钟信号。 外部测试仪生成的相移时钟信号可用于产生对准的高频信号以代替由锁相环生成的信号。 多个相移的测试仪产生的时钟信号可以经受用于产生输入/输出和核心时钟替换信号的异或运算。 从测试仪接收的时钟信号也可以对齐。 因此，在进入旁路模式之前可以补偿各种偏差。 在本发明的一些实施例中，核心和I / O PLL时钟用于在建立阶段建立对准，在其它实施例中，核心和I / O PLL根本不需要被利用以产生适当的内部时钟 来自外部测试仪的信号。

    Multiple VCO phase lock loop architecture
    9.
    发明授权
    Multiple VCO phase lock loop architecture 有权
    多个VCO锁相环结构

    公开(公告)号：US06670833B2

    公开(公告)日：2003-12-30

    申请号：US10052264

    申请日：2002-01-23

    Applicant: Nasser A. Kurd ,  Ian Young

    Inventor： Nasser A. Kurd ,  Ian Young

    IPC: H03L706

    CPC classification number: H03L7/0893 ,  H03L7/0896 ,  H03L7/099 ,  Y10S331/02

    Abstract: A VCO phase lock loop system may include a first voltage controlled oscillator that provides a first oscillation signal relative to a first frequency and a second voltage controlled oscillator that provide a second oscillation signal relative to a second frequency. A loop filter capacitor may be associated with both the first voltage controlled oscillator and the second voltage controlled oscillator. A selection device may enable components associated with the either one of the voltage controlled oscillators while disabling components associated with the other one of the voltage controlled oscillators.

    Abstract translation: VCO锁相环系统可以包括提供相对于第一频率的第一振荡信号的第一压控振荡器和相对于第二频率提供第二振荡信号的第二压控振荡器。 环路滤波电容器可以与第一压控振荡器和第二压控振荡器两者相关联。 选择装置可以启用与压控振荡器中的任一个相关联的组件，同时禁用与压控振荡器中的另一个相关联的组件。

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