公开(公告)号：US08278705B2

公开(公告)日：2012-10-02

申请号：US13152041

申请日：2011-06-02

申请人： Nathan Kraft

发明人： Nathan Kraft

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

摘要翻译： 场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。 多个沟槽包括多个门控沟槽和多个非门控沟槽。 第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。 电介质材料填充每个门控沟槽和非门控沟槽的底部。 栅极电极设置在每个门控沟槽中。 第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

公开(公告)号：US07955920B2

公开(公告)日：2011-06-07

申请号：US12822008

申请日：2010-06-23

申请人： Nathan Kraft

发明人： Nathan Kraft

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches include a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

摘要翻译： 场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。 多个沟槽包括多个门控沟槽和多个非门控沟槽。 第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。 电介质材料填充每个门控沟槽和非门控沟槽的底部。 栅极电极设置在每个门控沟槽中。 第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

公开(公告)号：US07473603B2

公开(公告)日：2009-01-06

申请号：US11938583

申请日：2007-11-12

申请人： Nathan Kraft ,  Christopher Boguslaw Kocon ,  Paul Thorup

发明人： Nathan Kraft ,  Christopher Boguslaw Kocon ,  Paul Thorup

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7811

摘要： A method of forming a field effect transistor includes the following steps. A trench is formed in a semiconductor region, and a shield dielectric layer lining lower sidewalls and a bottom surface of the trench is formed. A shield electrode is formed in a lower portion of the trench, and a dielectric layer is formed along upper trench sidewalls and over the shield electrode. A gate electrode is formed in the trench over the shield electrode, and an interconnect layer connecting the gate electrode and the shield electrode is formed.

摘要翻译： 形成场效应晶体管的方法包括以下步骤。 在半导体区域中形成沟槽，并形成衬套下侧壁和沟槽底面的屏蔽电介质层。 屏蔽电极形成在沟槽的下部，并且沿上沟槽侧壁和屏蔽电极上方形成电介质层。 在屏蔽电极上的沟槽中形成栅电极，形成连接栅电极和屏蔽电极的互连层。

公开(公告)号：US07393749B2

公开(公告)日：2008-07-01

申请号：US11450903

申请日：2006-06-08

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L21/336 ,  H01L23/62

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant of dopants of the first conductivity type is carried out to thereby form a region of first conductivity type along the trench sidewalls. A threshold voltage adjust implant of dopants of the second conductivity type is carried out to thereby convert a conductivity type of a portion of the region of first conductivity type extending along upper sidewalls of the trench to the second conductivity type. Source regions of the first conductivity type flanking each side of the trench are formed.

摘要翻译： 场效应晶体管如下形成。 提供了具有在半导体区域上延伸的具有第二导电性的外延层的第一导电类型的半导体区域。 形成延伸穿过外延层并终止在半导体区域中的沟槽。 执行第一导电类型的掺杂剂的双向成角度注入，从而沿着沟槽侧壁形成第一导电类型的区域。 执行阈值电压调整第二导电类型的掺杂剂的注入，从而将沿沟槽的上侧壁延伸的第一导电类型区域的一部分的导电类型转换为第二导电类型。 形成沟槽每一侧的第一导电类型的源区。

公开(公告)号：US20070173021A1

公开(公告)日：2007-07-26

申请号：US11339998

申请日：2006-01-25

申请人： Christopher Kocon ,  Nathan Kraft

发明人： Christopher Kocon ,  Nathan Kraft

IPC分类号： H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： PATENT A trench gate FET is formed as follows. A well region is formed in a silicon region. A plurality of active gate trenches and a termination trench are simultaneously formed in an active region and a termination region of the FET, respectively, such that the well region is divided into a plurality of active body regions and a termination body region. Using a mask, openings are formed over the termination body region and the active body region. Dopants are implanted into the active body regions and the termination body region through the openings thereby forming a first region in each active and termination body region. Exposed surfaces of all first regions are recessed so as to form a bowl-shaped recess having slanted walls and a bottom protruding through the first region such that remaining portions of the first region in each active body region form source regions that are self-aligned to the active gate trenches.

摘要翻译： 沟道栅FET如下形成。 阱区域形成在硅区域中。 多个有源栅极沟槽和端接沟槽分别同时形成在FET的有源区域和端接区域中，使得阱区域被分成多个有源体区域和端接体区域。 使用掩模，在终端体区域和活动体区域上形成开口。 通过开口将掺杂剂注入活性体区域和终端体区域，从而在每个活性和终止体区域中形成第一区域。 所有第一区域的露出的表面是凹进的，从而形成具有倾斜壁和通过第一区域突出的底部的碗状凹部，使得每个活性体区域中的第一区域的剩余部分形成自对准的源区域 有源栅极沟槽。

公开(公告)号：US20070032020A1

公开(公告)日：2007-02-08

申请号：US11479117

申请日：2006-06-29

申请人： Thomas Grebs ,  Nathan Kraft ,  Rodney Ridley ,  Gary Dolny ,  Joseph Yedinak ,  Christopher Kocon ,  Ashok Challa

发明人： Thomas Grebs ,  Nathan Kraft ,  Rodney Ridley ,  Gary Dolny ,  Joseph Yedinak ,  Christopher Kocon ,  Ashok Challa

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.

摘要翻译： 场效应晶体管如下形成。 在半导体区域中形成沟槽。 形成衬在沟槽侧壁和底部的电介质层。 沟槽填充有导电材料。 导电材料凹陷到沟槽中，从而在沟槽的底部形成屏蔽电极。 导电材料的凹陷包括导电材料的各向同性蚀刻。 在凹形屏蔽电极上形成电极间电介质（IED）。

公开(公告)号：US20050167742A1

公开(公告)日：2005-08-04

申请号：US11026276

申请日：2004-12-29

申请人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

IPC分类号： G06F1/26 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/336 ,  H01L21/68 ,  H01L23/495 ,  H01L23/498 ,  H01L29/06 ,  H01L29/165 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H02M3/00 ,  H02M3/335

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

摘要翻译： 公开了用于改进的功率器件的各种实施例及其制造方法，封装和结合其的用于各种功率电子应用的电路。 本发明的一个方面结合了许多电荷平衡技术和用于减小寄生电容的其它技术，以获得具有改进的电压性能，较高开关速度和较低导通电阻的功率器件的不同实施例。 本发明的另一方面提供了用于低，中和高电压装置的改进的端接结构。 根据本发明的其它方面提供了改进的功率器件制造方法。 提出了具体的处理步骤的改进，例如沟槽的形成，沟槽内的电介质层的形成，台面结构的形成以及用于降低衬底厚度的工艺等。 根据本发明的另一方面，电荷平衡功率器件在同一管芯上并入温度和电流检测元件，例如二极管。 本发明的其它方面改进了用于功率器件的等效串联电阻（ESR），在与功率器件相同的芯片上并入附加电路，并提供对电荷平衡功率器件的封装的改进。

公开(公告)号：US20100258855A1

公开(公告)日：2010-10-14

申请号：US12822008

申请日：2010-06-23

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches include a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

摘要翻译： 场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。 多个沟槽包括多个门控沟槽和多个非门控沟槽。 第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。 电介质材料填充每个门控沟槽和非门控沟槽的底部。 栅极电极设置在每个门控沟槽中。 第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

公开(公告)号：US20100038708A1

公开(公告)日：2010-02-18

申请号：US12582487

申请日：2009-10-20

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.

摘要翻译： 形成电荷平衡MOSFET的方法包括以下步骤。 提供了具有第一导电类型的上覆外延层的衬底。 形成延伸穿过外延层并终止在衬底内的栅极沟槽。 形成栅极沟槽的侧壁和底表面的屏蔽电介质。 在栅极沟槽中形成屏蔽电极。 栅极电介质层沿栅极沟槽的上侧壁形成。 栅电极形成在栅极沟槽中，使得栅电极延伸过去但与屏蔽电极绝缘。 形成延伸穿过外延层并终止于衬底内的深凹坑，使得深凹坑与栅沟槽横向间隔开。 深凹坑填充有第二导电类型的硅材料。

公开(公告)号：US07625799B2

公开(公告)日：2009-12-01

申请号：US12418949

申请日：2009-04-06

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L21/336 ,  H01L23/62

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion. A two-pass angled implant of dopants of the first conductivity type is carried out to form a silicon region of first conductivity type along sidewalls of the lower trench portion, while the protective material blocks the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion.

摘要翻译： 提供了具有在半导体区域上延伸的外延层的半导体区域。 执行第一硅蚀刻以形成延伸到外延层内并在外延层内终止的上沟槽部分。 沿着上沟槽部分的侧壁以及与上沟槽部分相邻的台面区域，而不是沿着上沟槽部分的底表面延伸形成保护材料。 执行第二硅蚀刻以形成从上沟槽部分的底表面延伸穿过外延层并终止在半导体区域内的下沟槽部分，使得下沟槽部分比上沟槽部分窄。 执行第一导电类型的掺杂剂的双向成角度注入，以形成沿着下沟槽部分的侧壁的第一导电类型的硅区域，而保护材料阻挡注入掺杂剂进入上沟槽部分的侧壁 以及与上沟槽部分相邻的台面区域。