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公开(公告)号：US10673648B1
公开(公告)日：2020-06-02
申请号：US16358514
申请日：2019-03-19
IPC分类号： H04L12/40 , G06F13/42 , H04L12/823 , H04L29/06 , H04L12/801
摘要： A network device includes a Network Interface Device (NID) and multiple servers. Each server is coupled to the NID via a corresponding PCIe bus. The NID has a network port through which it receives packets. The packets are destined for one of the servers. The NID detects a PCIe congestion condition regarding the PCIe bus to the server. Rather than transferring the packet across the bus, the NID buffers the packet and places a pointer to the packet in an overflow queue. If the level of bus congestion is high, the NID sets the packet's ECN-CE bit. When PCIe bus congestion subsides, the packet passes to the server. The server responds by returning an ACK whose ECE bit is set. The originating TCP endpoint in turn reduces the rate at which it sends data to the destination server, thereby reducing congestion at the PCIe bus interface within the network device.
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2.发明授权公开(公告)号：US10230638B2
公开(公告)日：2019-03-12
申请号：US16042339
申请日：2018-07-23
发明人： Gavin J. Stark , Stuart C. Wray
IPC分类号： H04L12/741 , H04L29/06
摘要： An integrated circuit includes a processor and an exact-match flow table structure. A first packet is received onto the integrated circuit. The packet is determined to be of a first type. As a result of this determination, execution by the processor of a first sequence of instructions is initiated. This execution causes bits of the first packet to be concatenated and modified in a first way, thereby generating a first Flow Id. The first Flow Id is an exact-match for the Flow Id of a first stored flow entry. A second packet is received. It is of a first type. As a result, a second sequence of instructions is executed. This causes bits of the second packet to be concatenated and modified in a second way, thereby generating a second Flow Id. The second Flow Id is an exact-match for the Flow Id of a second stored flow entry.
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公开(公告)号：US20180332374A1
公开(公告)日：2018-11-15
申请号：US16042572
申请日：2018-07-23
发明人： J. Niel Viljoen
IPC分类号： H04Q11/00
摘要： An array of columns and rows of host server devices is mounted in a row of racks. Each device has a host processor and an exact-match packet switching integrated circuit. Packets are switched within the system using exact-match flow tables that are provisioned by a central controller. Each device is coupled by a first cable to a device to its left, by a second cable to a device to its right, by a third cable to a device above, and by a fourth cable to a device below. In one example, substantially all cables that are one meter or less in length are non-optical cables, whereas substantially all cables that are seven meters or more in length are optical cables. Advantageously, each device of a majority of the devices has four and only four cable ports, and connects only to non-optical cables, and the connections involve no optical transceiver.
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4.发明授权公开(公告)号：US10069767B1
公开(公告)日：2018-09-04
申请号：US14928493
申请日：2015-10-30
发明人： Ron L. Swartzentruber , Rick Bouley
IPC分类号： G06F13/40 , G06F13/36 , G06F13/00 , H04L12/861 , H04L12/879
摘要： A method of dynamically allocating buffers involves receiving a packet onto an ingress circuit. The ingress circuit includes a memory that stores a free buffer list, and an allocated buffer list. Packet data of the packet is stored into a buffer. The buffer is associated with a buffer identification (ID). The buffer ID is moved from the free buffer list to the allocated buffer list once the packet data is stored in the buffer. The buffer ID is used to read the packet data from the buffer and into an egress circuit and is stored in a de-allocation buffer list in the egress circuit. A send buffer IDs command is received from a processor onto the egress circuit and instructs the egress circuit to send the buffer ID to the ingress circuit such that the buffer ID is pushed onto the free buffer list.
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公开(公告)号：US10032119B1
公开(公告)日：2018-07-24
申请号：US14579458
申请日：2014-12-22
IPC分类号： H04L12/863 , G06Q10/02 , G06F12/06
摘要： An ordering system receives release requests to release packets, where each packet has an associated sequence number, but the system only releases packets sequentially in accordance with the sequence numbers. The system includes a Ticket Order Release Command Dispatcher And Sequence Number Translator (TORCDSNT) and a plurality of Ticket Order Release Bitmap Blocks (TORBBs). The TORBBs are stored in one or more transactional memories. In response to receiving release requests, the TORCDSNT issues atomic ticket release commands to the transactional memory or memories, and uses the multiple TORBBs in a chained manner to implement a larger overall ticket release bitmap than could otherwise be supported by any one of the TORBBs individually. Special use of one flag bit position in each TORBB facilitates this chaining. In one example, the system is implemented in a network flow processor so that the TORBBs are maintained in transactional memories spread across the chip.
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公开(公告)号：US10031878B2
公开(公告)日：2018-07-24
申请号：US15463857
申请日：2017-03-20
发明人： Gavin J. Stark
摘要： An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. A configurable mesh data bus includes a command mesh, a pull-id mesh, and two data meshes. The configurable mesh data bus extends through all the islands. For each mesh, each island includes a centrally located crossbar switch and eight half links. Two half links extend to ports on the top edge of the island, a half link extends to a port on a right edge of the island, two half links extend to ports on the bottom edge of the island, and a half link extents to a port on the left edge of the island. Two additional links extend to functional circuitry of the island. The configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit.
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公开(公告)号：US09990307B1
公开(公告)日：2018-06-05
申请号：US14527642
申请日：2014-10-29
发明人： Chirag P. Patel , Salma Mirza
IPC分类号： G06F12/10 , G06F12/1081 , G06F13/30 , H04L12/40
CPC分类号： G06F12/1081 , G06F13/30 , H04L12/40071
摘要： Packet information is stored in split fashion such that a first part is stored in a first device and a second part is stored in a second device. A split packet transmission DMA engine receives an egress packet descriptor. The descriptor does not indicate where the second part is stored but contains information about the first part. Using this information, the DMA engine causes a part of the first part to be transferred from the first device to the DMA engine. Address information in the first part indicates where the second part is stored. The DMA engine uses the address information to cause the second part to be transferred from the second device to the DMA engine. When both the part of the first part and the second part are stored in the DMA engine, then the entire packet is transferred in ordered fashion to an egress device.
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公开(公告)号：US09899996B1
公开(公告)日：2018-02-20
申请号：US14556135
申请日：2014-11-29
发明人： Gavin J. Stark , Bruce A. Wilford
CPC分类号： H03K17/00 , G06F9/467 , G06F13/40 , H04L45/745 , H04L45/748
摘要： A hardware trie structure includes a tree of internal node circuits and leaf node circuits. Each internal node is configured by a corresponding multi-bit node control value (NCV). Each leaf node can output a corresponding result value (RV). An input value (IV) supplied onto input leads of the trie causes signals to propagate through the trie such that one of the leaf nodes outputs one of the RVs onto output leads of the trie. In a transactional memory, a memory stores a set of NCVs and RVs. In response to a lookup command, the NCVs and RVs are read out of memory and are used to configure the trie. The IV of the lookup is supplied to the input leads, and the trie looks up an RV. A non-final RV initiates another lookup in a recursive fashion, whereas a final RV is returned as the result of the lookup command.
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9.发明申请公开(公告)号：US20170357594A1
公开(公告)日：2017-12-14
申请号：US15688937
申请日：2017-08-29
发明人： Gavin J. Stark , Rolf Neugebauer
IPC分类号： G06F12/109 , G06F9/46 , G06F13/38 , G06F12/1081
CPC分类号： G06F9/467 , G06F12/1081 , G06F12/109 , G06F13/385 , G06F2212/657 , G06F2213/0026
摘要： A transactional memory receives a command, where the command includes an address and a novel GAA (Generate Alert On Action) bit. If the GAA bit is set and if the transactional memory is enabled to generate alerts and if the command is a write into a memory of the transactional memory, then the transactional memory outputs an alert in accordance with preconfigured parameters. For example, the alert may be preconfigured to carry a value or key usable by the recipient of the alert to determine the reason for the alert. The alert may be set up to include the address of the memory location in the transactional memory that was written. The transactional memory may be set up to send the alert to a predetermined destination. The outputting of the alert may be a writing of information into a predetermined destination, or may be an outputting of an interrupt signal.
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10.发明授权公开(公告)号：US09819585B1
公开(公告)日：2017-11-14
申请号：US14726428
申请日：2015-05-29
发明人： Gavin J. Stark , Stuart C. Wray
IPC分类号： H04L12/701 , H04L12/741 , H04L29/06
CPC分类号： H04L45/745 , H04L49/00 , H04L69/22
摘要： An exact-match flow table structure stores flow entries. Each flow entry includes a Flow Id. A flow entry is generated from an incoming packet. The flow table structure determines whether there is a stored flow entry, the Flow Id of which is an exact-match for the generated Flow Id. In one novel aspect, a programmable reduce table circuit is used to generate a Flow Id. A selected subset of bits of an incoming packet is supplied as an address to an SRAM, so that the SRAM outputs a data value. The data value is supplied to a programmable lookup circuit such that the lookup circuit performs a selected type of lookup operation, and outputs a result value of a reduced number of bits. A multiplexer circuit is used to form a Flow Id such that the result value is a part of the Flow Id.
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