公开(公告)号：US20060178004A1

公开(公告)日：2006-08-10

申请号：US11053610

申请日：2005-02-08

申请人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes

发明人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes

IPC分类号： H01L21/4763

CPC分类号： B81C1/00476 ,  B81B2203/0118 ,  B81C2201/0132 ,  G01N1/32 ,  Y10S438/933

摘要： A method of patterning and releasing chemically sensitive low k films without the complication of a permanent hardmask stack, yielding an unaltered free-standing structure is provided. The method includes providing a structure including a Si-containing substrate having in-laid etch stop layers located therein; forming a chemically sensitive low k film and a protective hardmask having a pattern atop the structure; transferring the pattern to the chemically sensitive low k film to provide an opening that exposes a portion of the Si-containing substrate; and etching the exposed portion of the Si-containing substrate through the opening to provide a cavity in the Si-containing substrate in which a free-standing low k film structure is formed, while removing the hardmask. In accordance with the present invention, the etching comprises a XeF2 etch gas.

摘要翻译： 提供了图案化和释放化学敏感性低k膜的方法，而不需要永久性硬掩模堆叠的复杂性，产生未改变的独立结构。 该方法包括提供包括其中位于其中的内置蚀刻停止层的含Si衬底的结构; 形成化学敏感的低k膜和在结构顶部具有图案的保护性硬掩模; 将图案转移到化学敏感的低k膜上以提供暴露一部分含Si衬底的开口; 并且通过所述开口蚀刻含Si衬底的暴露部分，以在去除硬掩模的同时在其中形成独立的低k膜结构的含Si衬底中提供空腔。 根据本发明，蚀刻包括XeF 2 N 2蚀刻气体。

公开(公告)号：US07426067B1

公开(公告)日：2008-09-16

申请号：US10322195

申请日：2002-12-17

申请人： Victor M. Bright ,  Jeffrey Elam ,  Francois Fabreguette ,  Steven M. George ,  Nils Hoivik ,  Yung-Cheng Lee ,  Ryan Linderman ,  Marie Tripp

发明人： Victor M. Bright ,  Jeffrey Elam ,  Francois Fabreguette ,  Steven M. George ,  Nils Hoivik ,  Yung-Cheng Lee ,  Ryan Linderman ,  Marie Tripp

IPC分类号： G02B26/08

CPC分类号： B81C1/0096 ,  B81B3/0005 ,  B81B2207/115 ,  B81C1/00674 ,  B81C2201/112 ,  Y10S359/90

摘要： A micro-electromechanical device or MEMS having a conformal layer of material deposited by atomic layer deposition is discussed. The layer may provide physical protection to moving components of the device, may insulate electrical components of the device, may present a biocompatible surface interface to a biological system, and may otherwise improve such devices. The layer may also comprise a combination of multiple materials each deposited with great control to allow creating layers of customizable properties and to allow creating layers having multiple independent functions, such as providing physical protection from wear and providing electrical insulation.

摘要翻译： 讨论了具有通过原子层沉积沉积的材料的保形层的微机电装置或MEMS。 该层可以为装置的移动部件提供物理保护，可以使装置的电气部件绝缘，可以向生物系统提供生物相容的表面界面，并且可以改进这种装置。 该层还可以包括多种材料的组合，每种材料沉积有很大的控制以允许产生可定制性质的层，并且允许产生具有多个独立功能的层，例如提供物理保护免受磨损和提供电绝缘。

公开(公告)号：US20080067683A1

公开(公告)日：2008-03-20

申请号：US11871533

申请日：2007-10-12

申请人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

发明人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

IPC分类号： H01L23/48

CPC分类号： H01L21/306 ,  H01L21/32135 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76865 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01002 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01054 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/00

摘要： Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

公开(公告)号：US20120321907A1

公开(公告)日：2012-12-20

申请号：US13582131

申请日：2011-03-01

申请人： Nils Hoivik ,  Birger Stark ,  Anders Elfing ,  Kaiying Wang

发明人： Nils Hoivik ,  Birger Stark ,  Anders Elfing ,  Kaiying Wang

IPC分类号： B23K31/02 ,  B23K20/10 ,  B32B15/00 ,  B23K20/22

CPC分类号： B81C1/00269 ,  B81C2203/0118 ,  B81C2203/035 ,  H01L21/50 ,  H01L23/10 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/276 ,  H01L2224/29011 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/83007 ,  H01L2224/83193 ,  H01L2224/83204 ,  H01L2224/83207 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/164 ,  Y10T428/12493 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A metal inter-diffusion bonding method for forming hermetically sealed wafer-level packaging for MEMS devices. A stack of a first metal is provided on a surface of both a first wafer and a second wafer, the first metal being susceptible to oxidation in air; providing a layer of a second metal, having a melting point lower than that of the first metal, on an upper surface of each stack of the first metal, the layer of second metal being sufficiently thick to inhibit oxidation of the upper surface of the first metal; bringing the layer of the second metal on the first wafer into contact with the layer of second metal on the second wafer to form a bond interface; and applying a bonding pressure to the first and second wafers at a bonding temperature lower than the melting point of the second metal to initiate a bond, the bonding pressure being sufficient to deform the layers of the second metal at the bond interface.

摘要翻译： 一种用于形成用于MEMS器件的密封晶片级封装的金属互扩散接合方法。 在第一晶片和第二晶片的表面上设置第一金属的堆叠，第一金属容易在空气中氧化; 在第一金属的每个堆叠的上表面上提供具有低于第一金属的熔点的第二金属层，第二金属层足够厚以抑制第一金属的上表面的氧化 金属; 使第一晶片上的第二金属层与第二晶片上的第二金属层接触以形成键合界面; 以及在低于所述第二金属的熔点的接合温度下对所述第一和第二晶片施加结合压力以引发结合，所述接合压力足以使所述第二金属的所述层在所述键合界面处变形。

公开(公告)号：US20070195501A1

公开(公告)日：2007-08-23

申请号：US11358501

申请日：2006-02-21

申请人： Nils Hoivik ,  Ryan Linderman

发明人： Nils Hoivik ,  Ryan Linderman

IPC分类号： H05K7/20

CPC分类号： H01L23/42 ,  H01L23/3733 ,  H01L23/3737 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/8385 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

摘要： Integrated circuit-chip hot spot temperatures are reduced by providing localized regions of higher thermal conductivity in the conductive material interface at pre-designed locations by controlling how particles in the thermal paste stack- or pile-up during the pressing or squeezing of excess material from the interface. Nested channels are used to efficiently decrease the thermal resistance in the interface, by both allowing for the thermally conductive material with a higher particle volumetric fill to be used and by creating localized regions of densely packed particles between two surfaces.

摘要翻译： 通过在预先设计的位置通过控制在多余材料的挤压或挤压过程中如何将热糊料中的颗粒堆积或堆积，从而在导电材料界面中提供较高导热性的局部区域，从而降低集成电路芯片的热点温度 界面。 使用嵌套通道来有效地降低界面中的热阻，通过两者允许使用具有较高的颗粒体积填充的导热材料并且通过在两个表面之间产生密集填充的颗粒的局部区域。

公开(公告)号：US20080066860A1

公开(公告)日：2008-03-20

申请号：US11871504

申请日：2007-10-12

申请人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

发明人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

IPC分类号： C23F1/00

CPC分类号： H01L21/306 ,  H01L21/32135 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76865 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01002 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01054 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/00

摘要： Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

摘要翻译： 公开了一种在电介质层上处理包括衬底，电介质层和TaN-Ta衬垫的类型的半导体结构的方法和系统。 该方法包括使用XeF 2将至少一部分TaN-Ta衬套完全去除到介电层的步骤。 在优选实施例中，本发明使用XeF2选择性气相蚀刻作为Ta-TaN化学机械抛光（CMP）的替代品作为基本的“衬垫去除工艺”，并且作为“选择性电镀镀层去除工艺”。 在第一次使用中，XeF2用于在铜CMP之后去除金属衬垫TaN-Ta。 在第二次使用中，XeF2蚀刻用于选择性地去除用于在铜导体上形成金属覆盖层的电镀基底（TaN-Ta）。

公开(公告)号：US20060189134A1

公开(公告)日：2006-08-24

申请号：US11064561

申请日：2005-02-24

申请人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

发明人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/306 ,  H01L21/32135 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76865 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01002 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01054 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/00

摘要： Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.