-
公开(公告)号：US11595052B2
公开(公告)日：2023-02-28
申请号：US17623613
申请日：2019-07-26
发明人： Ting Li , Gangyi Hu , Ruzhang Li , Yong Zhang , Dongbing Fu , Zhengbo Huang , Yabo Ni , Jian'an Wang , Guangbing Chen
摘要： A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.
-
公开(公告)号：US11595004B2
公开(公告)日：2023-02-28
申请号：US17057698
申请日：2019-05-13
发明人： Ting Li , Zhengbo Huang , Yong Zhang , Yabo Ni , Jian'an Wang , Dongbing Fu
摘要： A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.
-
公开(公告)号：US11502657B2
公开(公告)日：2022-11-15
申请号：US17040516
申请日：2018-07-25
发明人： Xiaofeng Shen , Xingfa Huang , Liang Li , Xi Chen , Mingyuan Xu , Jian'an Wang , Dongbing Fu , Guangbing Chen
摘要： A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.
-
公开(公告)号：US20220247423A1
公开(公告)日：2022-08-04
申请号：US17616643
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
发明人： DAIGUO XU , HEQUAN JIANG , RUZHANG LI , JIANAN WANG , GUANGBING CHEN , YUXIN WANG , DONGBING FU , LIANG LI , YAN WANG
摘要： SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.
-
5.发明授权公开(公告)号：US11115039B2
公开(公告)日：2021-09-07
申请号：US17057702
申请日：2019-05-13
发明人： Ting Li , Zhengbo Huang , Yong Zhang , Yabo Ni , Jian'an Wang , Dongbing Fu
摘要： The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.
-
6.发明申请公开(公告)号：US20210203344A1
公开(公告)日：2021-07-01
申请号：US17057702
申请日：2019-05-13
发明人： Ting LI , Zhengbo HUANG , Yong ZHANG , Yabo NI , Jian'an WANG , Dongbing FU
IPC分类号： H03M1/12 , G01R19/165 , H03M1/54
摘要： The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.
-
公开(公告)号：US10778092B2
公开(公告)日：2020-09-15
申请号：US16605804
申请日：2017-09-11
发明人： Rongbin Hu , Yonglu Wang , Zhengping Zhang , Jian'an Wang , Guangbing Chen , Dongbing Fu , Yuxin Wang , Hequan Jiang , Gangyi Hu
摘要： The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.
-
公开(公告)号：US20200011911A1
公开(公告)日：2020-01-09
申请号：US16493184
申请日：2017-07-21
发明人： Yingtai LI , Gangyi HU , Luncai LIU , Fan LIU , Jian'an WANG , Xin LEI , Xiaozong HUANG , Guoqiang WANG , Jin ZHAO , Jianzhuang LI
IPC分类号： G01R23/02
摘要： A high-precision frequency measuring system and method. The system includes: an analog-to-digital conversion module for receiving an analog intermediate frequency signal to convert the analog intermediate frequency signal into a digital intermediate frequency signal; a frequency mixing module for generating two orthogonal local carriers to convert the digital intermediate frequency signal to a digital baseband signal; an extraction filter module for performing low-pass filtering and extraction of the digital baseband signal, so as to reduce a data rate; a Fourier transform module for obtaining a frequency domain signal; a frequency measurement module for obtaining a first frequency measurement value; a scanning module for obtaining a scanned second frequency measurement value; and a selector for selecting either the first frequency measurement value or the second frequency measurement value as a result of frequency measurement. The system and method can improve the accuracy of frequency measurement.
-
公开(公告)号：US10425065B2
公开(公告)日：2019-09-24
申请号：US16064658
申请日：2017-01-19
发明人： Daiguo Xu , Gangyi Hu , Ruzhang Li , Jianan Wang , Guangbing Chen , Yuxin Wang , Dongbing Fu , Tao Liu , Lu Liu , Minming Deng , Hanfu Shi , Xu Wang
摘要： A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.
-
公开(公告)号：US11558064B2
公开(公告)日：2023-01-17
申请号：US17616643
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
发明人： Daiguo Xu , Hequan Jiang , Ruzhang Li , Jianan Wang , Guangbing Chen , Yuxin Wang , Dongbing Fu , Liang Li , Yan Wang
摘要： SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.
-
-
-
-
-
-
-
-
-
搜索结果
48 条记录 (耗时 0.027 秒)